Microchip dsPIC33FJ06GS001 Manual

Microchip Ikke kategoriseret dsPIC33FJ06GS001

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2008-2017 Microchip Technology Inc. DS70000323H-page 1
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0 Introduction ....................................................................................................................... 2
2.0 Features............................................................................................................................ 3
3.0 Control Registers .............................................................................................................. 4
4.0 Architecture Overview..................................................................................................... 34
5.0 Module Description ......................................................................................................... 37
6.0 PWM Generator .............................................................................................................. 48
7.0 PWM Triggers ................................................................................................................. 62
8.0 PWM Interrupts............................................................................................................... 69
9.0 PWM Operating Modes................................................................................................... 70
10.0 PWM Fault Pins .............................................................................................................. 75
11.0 Special Features ............................................................................................................. 87
12.0 PWM Output Pin Control................................................................................................. 95
13.0 Immediate Update of PWM Duty Cycle .......................................................................... 98
14.0 Power-Saving Modes...................................................................................................... 99
15.0 External Control of Individual Time Base(s) (Current Reset Mode) .............................. 100
16.0 Application Information ................................................................................................. 101
17.0 PWM Interconnects with Other Peripherals .................................................................. 115
18.0 Related Application Notes............................................................................................. 118
19.0 Revision History............................................................................................................ 119
High-Speed PWM Module
dsPIC33/PIC24 Family Reference Manual
DS70000323H-page 2 2008-2017 Microchip Technology Inc.
1.0 INTRODUCTION
This section describes the High-Speed PWM module and its associated operational modes. The
High-Speed PWM module supports a wide variety of PWM modes and is ideal for power
conversion applications. Some of the common applications that the High-Speed PWM module
supports are:
• AC-to-DC Converters
• Power Factor Correction (PFC)
• Interleaved Power Factor Correction (IPFC)
• Inverters
• DC-to-DC Converters
• Battery Chargers
• Digital Lighting
• Uninterruptable Power Supply (UPS)
• AC and DC Motors
• Resonant Converters
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33/PIC24 devices.
Please consult the note at the beginning of the “High-Speed PWM” chapter in the
current device data sheet to check whether this document supports the device you
are using.
Device data sheets and family reference manual sections are available for download
from the Microchip Worldwide Web site at: http://www.microchip.com.
dsPIC33/PIC24 Family Reference Manual
DS70000323H-page 8 2008-2017 Microchip Technology Inc.
bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits
( )1
1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event
Register 3-1: PTCON: PWMx Time Base Control Register (Continued)
Note 1: These bits should be changed only when PTEN = 0.
2: The PWM time base synchronization must only be used in the master time base with no phase shifting.
3: When the PWM module is enabled by setting PTCON<15> = 1, a delay will be observed before the PWM
outputs start switching. This delay is equal to:
PWM Turn-on Delay = (2/ACLK) + (3 (PCLKDIV<2:0> Setting)/ACLK) + 15 ns
2008-2017 Microchip Technology Inc. DS70000323H-page 11
High-Speed PWM Module
Register 3-5: STCON: PWMx Secondary Master Time Base Control Register
U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — SESTAT SEIEN EIPU
( )1
SYNCPOL
( , )1 2
SYNCOEN
(1, )2
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN
(1,2)
SYNCSRC<2:0>
(1)
SEVTPS<3:0>
(1)
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 SESTAT: Special Event Trigger Interrupt Status bit
1 = Secondary Special Event Trigger interrupt is pending
0 = Secondary Special Event Trigger interrupt is not pending
This bit is cleared by setting SEIEN = 0.
bit 11 SEIEN: Special Event Trigger Interrupt Enable bit
1 = Secondary Special Event Trigger interrupt is enabled
0 = Secondary Special Event Trigger interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit
( )1
1 = Active Secondary Period register is updated immediately.
0 = Active Secondary Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
( , )1 2
1 = The falling edge of SYNCEN resets the SMTMR and the SYNCO2 output is active-low
0 = The rising edge of SYNCEN resets the SMTMR and the SYNCO2 output is active-high
bit 8 SYNCOEN: Secondary Master Time Base Sync Enable bit
( , )1 2
1 = SYNCO2 output is enabled
0 = SYNCO2 output is disabled
bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit
( , )1 2
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
bit 6-4 SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits
( )1
011 = SYNCI4
010 = SYNCI3
001 = SYNCI2
000 = SYNCI1
bit 3-0 SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits
( )1
1111 = 1:16 Postcale
•
•
•
0001 = 1:2 Postcale
0000 = 1:1 Postscale
Note 1: These bits should be changed only when PTEN = 0.
2: The PWM time base synchronization must only be used in the master time base with no phase shifting.
dsPIC33/PIC24 Family Reference Manual
DS70000323H-page 12 2008-2017 Microchip Technology Inc.
Register 3-6: STCON2: PWMx Secondary Clock Divider Select Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCLKDIV<2:0>
( ,1 2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 PCLKDIV<2:0>: PWM Input Secondary Clock Prescaler (Divider) Select bits
( , )1 2
111 = Reserved
110 = Divide-by-64, maximum PWM timing resolution
101 = Divide-by-32, maximum PWM timing resolution
100 = Divide-by-16, maximum PWM timing resolution
011 = Divide-by-8, maximum PWM timing resolution
010 = Divide-by-4, maximum PWM timing resolution
001 = Divide-by-2, maximum PWM timing resolution
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2: The PWM input clock prescaler will affect all timing parameters of the PWM module, including period, duty
cycle, phase shift, dead time, triggers, Leading-Edge Blanking (LEB) and PWM capture.
2008-2017 Microchip Technology Inc. DS70000323H-page 13
High-Speed PWM Module
Register 3-7: STPER: PWMx Secondary Master Time Base Period Register
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<15:8>
( , )1 2
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
STPER<7:0>
( , )1 2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 STPER<15:0>: PWM Secondary Master Time Base (SMTMR) Period Value bits
( , )1 2
Note 1: The PWM time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
2: Any period value that is less than 0x0028 must have the Least Significant 3 bits (LSbs) set to ‘0’. This
yields a period resolution of 8.32 ns (at the fastest Auxiliary Clock rate) for these very short PWM period
pulses.
Register 3-8: SSEVTCMP: PWMx Secondary Special Event Compare Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEVTCMP<12:5>
( , , )123
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
SSEVTCMP<4:0>
( , , )123
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 SSEVTCMP<12:0>: PWM Secondary Special Event Compare Count Value bits
( , , )123
bit 2-0 Unimplemented: Read as ‘0’
Note 1: 1 LSb = 1.04 ns; therefore, the minimum SSEVTCMP resolution is 8.32 ns at the fastest PWM clock
divider setting (STCON2<2:0> = 000).
2: The secondary Special Event Trigger is generated on a compare match with the PWM Secondary Master
Time Base Counter (SMTMR).
3: The SSEVTCMP<12:0> bits are used in conjunction with the STCON<3:0> bits field.
dsPIC33/PIC24 Family Reference Manual
DS70000323H-page 14 2008-2017 Microchip Technology Inc.
Register 3-9: CHOP: PWMx Chop Clock Generator Register
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CHPCLKEN — — — — — CHOPCLK<6:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
CHOPCLK<4:0> — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 14-10 Unimplemented: Read as ‘0’
bit 9-3 CHOPCLK<6:0>: Chop Clock Divider bits
Value in 8.32 ns increments. The frequency of the chop clock signal is calculated as follows:
Chop Frequency = 1/(16.64 * (CHOP<6:0> + 1) * Primary Master PWM Input Clock/PCLKDIV<2:0>)
bit 2-0 Unimplemented: Read as ‘0’
Register 3-10: MDC: PWMx Master Duty Cycle Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<15:8>
( , , )123
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<7:0>
( , , )123
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 MDC<15:0>: PWM Master Duty Cycle Value bits
( , , )123
Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,
while the maximum pulse width generated corresponds to a value of: Period + 0x0008.
2: MDC<15:0> < 0x0008 will produce a 0% duty cycle. MDC<15:0> > Period + 0x0008 will produce a
100% duty cycle.
3: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns to 40 ns, depending on the mode of
operation), the PWM duty cycle resolution will reduce from 1 LSb to 3 LSbs.
2008-2017 Microchip Technology Inc. DS70000323H-page 15
High-Speed PWM Module
Register 3-11: PWMCONx: PWMx Control Register
HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSTAT
( )1
CLSTAT
( )1
TRGSTAT FLTIEN CLIEN TRGIEN ITB
( )3
MDCS
( )3
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
DTC<1:0>
( )3
DTCP
( , )3 6
— MTBS CAM
( , , )235
XPRES
( , )4 7
IUE
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTSTAT: Fault Interrupt Status bit
( )1
1 = Fault interrupt is pending
0 = Fault interrupt is not pending
This bit is cleared by setting FLTIEN = 0.
bit 14 CLSTAT: Current-Limit Interrupt Status bit
( )1
1 = Current-limit interrupt is pending
0 = Current-limit interrupt is not pending
This bit is cleared by setting CLIEN = 0.
bit 13 TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = Trigger interrupt is not pending
This bit is cleared by setting TRGIEN = 0.
bit 12 FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11 CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared
bit 10 TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an IRQ
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9 ITB: Independent Time Base Mode bit
( )3
1 = PHASEx/SPHASEx registers provide the time base period for this PWM Generator
0 = PTPER/STPER registers provide timing for this PWM Generator
bit 8 MDCS: Master Duty Cycle Register Select bit
( )3
1 = MDC register provides duty cycle information for this PWM Generator
0 = PDCx and SDCx registers provide duty cycle information for this PWM Generator
Note 1: Software must clear the interrupt status and the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should not be changed after the PWM is enabled (PTEN = 1).
4: Configure FCLCONx<8> = 0 and PWMCONx<9> = 1 to operate in External Period Reset mode.
5: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase-Shift and Dead-Time
registers. The highest CAM resolution available is 8.32 ns with the clock prescaler set to the fastest clock.
6: DTC<1:0> = 11 for DTCP to be effective or else, the DTCP bit is ignored.
7: In the True Independent PWM Output mode (PMOD<1:0> = 11 and ITB = 1) with XPRES = 1, the PWM
Generator still requires the signal arriving at the PWMxH pin to be inactive to reset the PWM counter.

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Model: dsPIC33FJ06GS001

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