Microchip PL360B Manual
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PL360
PL360 Host Controller
Introduction
The PL360 is a multi-protocol modem for the Power Line Communication (PLC) device, implementing a very flexible
architecture and allowing the implementation of standard and customized PLC solutions. It has been conceived to be
bundled with an external Microchip MCU, which downloads the corresponding PLC firmware and controls the
operation of the PL360 device.
The purpose of the PL360 Host Controller is to provide the external microcontroller a way to control the PL360 device
and offer upper layers an easy way to get access to PLC communication.
As an example of the PLC system, the figure below shows the system architecture for G3 protocol based on a PL360
device being controlled by a SAM4C MCU.
Figure 1. G3 System Architecture
Embedded USI
G3-PLC Stack
PHY + PLC Transceiver
SAM4C
( ITU-T G.9903 )
( IEEE 802.15.4 )
( IETF RFC 4944 )
Adaptation Layer
MAC Layer
PAL Layer
sniffer_if
phy_if
mac_if
adp_if
app_if
Host Controller
PLC
USER APPLICATION
PL360
SPI
PLATFORM
IPv6 STACK
Detect
Interrupt
Carrier
The aim of this document is to clarify and detail the user interface of the PL360 Host Controller.
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 1
Features
• Compliant with PRIME 1.3 Physical Layer
• Compliant with PRIME 1.4 Physical Layer
• Compliant with G3 Physical Layer
• SPI Interface
• Secure Boot Option
PL360
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 2
8.1. PHY Examples........................................................................................................................... 32
9. Supported Platforms............................................................................................................................. 34
9.1. Supported MCU Families........................................................................................................... 34
9.2. Supported Transceivers............................................................................................................. 34
9.3. Supported Boards...................................................................................................................... 34
10. Abbreviations........................................................................................................................................ 35
11. References............................................................................................................................................36
12. PL360 Host Controller API.................................................................................................................... 37
12.1. Common PHY API......................................................................................................................37
12.2. G3 PHY API............................................................................................................................... 41
12.3. PRIME PHY SAP....................................................................................................................... 63
13. Appendix B: ZC Offset Configuration.................................................................................................... 83
14. Revision History.................................................................................................................................... 84
14.1. Rev A – 03/2018.........................................................................................................................84
14.2. Rev B - 10/2018......................................................................................................................... 84
14.3. Rev C - 04/2019......................................................................................................................... 84
14.4. Rev D - 07/2019......................................................................................................................... 85
14.5. Rev E - 08/2020......................................................................................................................... 85
The Microchip Website.................................................................................................................................86
Product Change Notification Service............................................................................................................86
Customer Support........................................................................................................................................ 86
Microchip Devices Code Protection Feature................................................................................................ 86
Legal Notice................................................................................................................................................. 87
Trademarks.................................................................................................................................................. 87
Quality Management System....................................................................................................................... 88
Worldwide Sales and Service.......................................................................................................................89
PL360
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 4
1. PL360 Host Controller Architecture
The PL360 Host Controller is a C source code component which provides the host MCU application access to the
API of the Power Line Communications PHY layer running in the PL360 device. shows the architecture ofFigure 1-1
the software which runs on the host MCU. The components of the PL360 Host Controller are described in the
following subsections.
Figure 1-1. PL360 Host Controller Architecture
HOST MCU
PLC Application
PLC Application Interface API
Bootloader PLC Stack Wrapper Add-ons
PL360 Host Controller
Hardware Abstracion Layer
1.1 PL360 Host Controller File Structure
The PL360 Host Controller is provided as a component of Microchip ASF (Advanced Software Framework). The
image below shows the location of the main files of the PL360 Host Controller Software. Different blocks provide
different features. The next subsections describe the purpose of each block.
PL360
PL360 Host Controller Architecture
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 5
• Use PIB objects specification. Please refer to or 12.2.5 PIB Objects Specification and Access (G3) 12.3.4 PIB
Objects Specification and Access (PRIME)
1.8 Debug Mode
In the Debug mode of the PL360, the core of the device and the peripherals are reset. In this mode, RAM memory is
still alive and the content of the memory is maintained, but the PL360 is set in Bootloader mode. The bootloader
commands are used to access the memory contents.
Reloading of the program is not necessary to return to the PL360 normal operating mode.
Some requirements are mandatory to handle this mode:
• The NRST pin of the PL360 device must be connected to a host device.
• The PL360 Control fuses must be configured to allow read operations. For further information, please refer to
the .PL360 datasheet
There are two different ways to manage Debug mode:
• Using standard API functions. Please refer to .12.1 Common PHY API
• Using PIB objects specification. Please refer to or 12.2.5 PIB Objects Specification and Access (G3) 12.3.4 PIB
Objects Specification and Access (PRIME)
Please contact Microchip Support for further information.
PL360
PL360 Host Controller Architecture
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 8
2. PL360 System Architecture
2.1 Block Diagram
Figure 2-1 shows the PL360 system architecture of the embedded firmware. The PL360 device has an embedded
Cortex® M7 CPU running the PLC firmware. This firmware can either implement the G3 or the PRIME Physical layer,
depending on what has been loaded by the PL360 Host Controller. The components of the system are described in
the following subsections.
Figure 2-1. PL360 Embedded Firmware Architecture
PL360 SoC
PHY Host Application
PHY
UTILS
TX
Chain
Coupling
PHY PLC Service
Application Interface (PHY API)
Bootloader
DACC
PL360 Drivers
ADCC SPI XDMAC XCORR PIO CRC
WDT SPU APMC
RX
Chain
Shared
Memory
Host
Interface
Zero
Cross
Program
Memory
Data
Memory
2.2 Bootloader
The bootloader is an Internal Peripheral (IP) designed to load the program from an external master into the
instruction memory of the Cortex M7. This IP can access the instruction memory, data memory and peripheral
registers.
For further information, please refer to the PL360 datasheet.
2.3 PL360 Memory
There are two memory configurations controlled via MEM_CONFIG bit. In the firmware loading process, the
appropriate memory configuration is established by the PL360 Host Controller according to the firmware requisites.
PL360
PL360 System Architecture
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 9
2.6 PHY Host Application
The PHY Host Application is responsible for running the main application of the PL360 device. It is in charge of
initializing the hardware and clock systems, checking the watchdog timer and managing the PL360 PLC service
described in the previous chapter.
PL360
PL360 System Architecture
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 11
3. Brief about ASF
The Advanced Software Framework (ASF) is a MCU software library providing a large collection of embedded
software for Microchip Flash MCUs: megaAVR, AVR XMEGA, AVR UC3 and SAM devices.
For details on ASF, please refer to the Advanced Software Framework documentation:
•Advanced Software Framework - Website
• [PDF] Atmel AVR4029: Atmel Software Framework - Getting Started
• [PDF] Atmel AVR4030: Atmel Software Framework - Reference Manual
PL360
Brief about ASF
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 12
4. Initialization Example
This chapter aims to explain the different steps required during the initialization phase of the system. After powering
up the PL360 device, a set of initialization sequences must be executed in the correct order for the proper operation
of the PL360 device.
The steps are the following:
1. Init controller descriptor
2. Set controller callbacks
3. Enable controller
4. PL360 event handling
CAUTION
Failure to complete any of the these initialization steps will result in failure in the PL360 Host Controller
startup.
4.1 Init Controller Descriptor
The PL360 Host Controller is initialized by calling the function in the API. The PL360 Host Controlleratpl360_init
initialization routine performs the following actions:
• Disable PLC interrupt and component
• Register wrapper for Hardware Abstraction Layer (for further information, please refer to 12.1.1 Initialization
Function)
• Reset the PL360 device using corresponding host MCU control GPIOs
• Configure a GPIO as an interrupt source from the PL360 device
• Initialize the SPI driver
• Register an internal event handler for the external PLC interrupt
• If an add-on is required, initialize specific add-on (configured previously). See chapter 5.1 Configure Application
• Return a descriptor to the PL360 Host Controller. This descriptor will be used to manage the PLC
communication
4.2 Set Controller Callbacks
After initializing the PL360 Host Controller, it is important to set callbacks to manage PL360 events.
The PL360 Host Controller reports PLC events using callback functions.
The following callback functions are defined:
• Data indication: Used to report a new incoming message
• Data confirm: Used to report the result of the last transmitted message
• Add-on event: Used to report that a new add-on message is ready to be sent to the PLC application
• Exception event: Used to report if an exception occurs, such as a reset of the PL360 device
• Sleep mode event: Used to report that Sleep mode has been disabled
• Debug mode event: Used to report that Debug mode has been disabled
4.3 Enable Controller
The PL360 Host Controller is enabled by calling the function in the API. This PL360 Hostatpl360_enable
Controller routine performs the following actions:
• Disable/enable PLC interrupt and component
PL360
Initialization Example
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 13
• Transfer the PL360 firmware to the PL360 device and validate. In case of failure, report a critical error in host
communication with the PL360 device through exception callback
4.4 PLC Event Handling
Once the controller callbacks have been set up, the PL360 Host Controller component must be enabled. Then, the
host MCU application is required to call the PL360 Host Controller API periodically to handle events from PL360
embedded firmware.
The PL360 Host Controller API allows the host MCU application to interact with the PL360 embedded firmware. To
facilitate interaction, the PL360 Host Controller implements the host interface protocol described in section 6. Host
Interface Management. This protocol defines how to serialize and how to handle API requests and response
callbacks over the SPI bus interface.
Some PL360 Host Controller APIs are synchronous function calls, whose return indicates that the requested action is
completed. However, most API functions are asynchronous. This means that when the application calls an API to
request a service, the call is non-blocking and returns immediately, usually before the requested action is completed.
When the requested action is completed, a notification is provided in the form of a host interface protocol message
from the PL360 embedded firmware to the PL360 Host Controller, which, in turn, delivers it to the application via
callback functions. Asynchronous operation is essential when the requested service, such as a PLC message
transmission, may take significant time to complete. In general, the PL360 embedded firmware uses asynchronous
events to notify the host driver of status changes or pending data.
The PL360 device interrupts the host MCU when one or more events are pending in the PL360 embedded firmware.
The host MCU application processes received data and events when the PL360 Host Controller calls the
corresponding event callback function(s). In order to receive event callbacks, the host MCU application is required to
periodically call the function in the API.atpl360_handle_events
When host MCU application calls , the PL360 Host Controller checks for pendingatpl360_handle_events
unhandled interrupts from the PL360 device. If no interrupt is pending, it returns immediately. If an interrupt is
pending, function dispatches the PLC event data to the respective registered callback. Ifatpl360_handle_events
the corresponding callback is not registered, the PLC event is discarded.
It is recommended to call this function either:
• From the main loop or from a dedicated task in the host MCU application; or,
• At least once when the host MCU application receives an interrupt from the PL360 embedded firmware
WARNING
The Host driver function is . In the operating systematpl360_handle_events non re-entrant
configuration, it is required to protect the PL360 Host Controller from re-entrance.
4.5 Code Example
The code example below shows the initialization flow as described in previous sections.
/**
* \brief Handler to receive add-on data from ATPL360.
*/
static void _handler_serial_atpl360_event(uint8_t *px_serial_data, uint16_t us_len)
{
/* customer application */
}
/**
* \brief Handler to receive add-on data from ATPL360.
*/
static void _handler_sleep_mode_resume_event(void)
{
/* customer application : restore PL360 custom configuration */
}
PL360
Initialization Example
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 14
/**
* \brief Main code entry point.
*/
int main( void )
{
atpl360_dev_callbacks_t x_atpl360_cbs;
atpl360_hal_wrapper_t x_atpl360_hal_wrp;
uint8_t uc_ret;
/* ASF function to setup clocking. */
sysclk_init();
/* ASF library function to setup for the evaluation kit being used. */
board_init();
/* Init ATPL360 */
x_atpl360_hal_wrp.plc_init = hal_plc_init;
x_atpl360_hal_wrp.plc_reset = hal_plc_reset;
x_atpl360_hal_wrp.plc_set_handler = hal_plc_set_handler;
x_atpl360_hal_wrp.plc_send_boot_cmd = hal_plc_send_boot_cmd;
x_atpl360_hal_wrp.plc_write_read_cmd = hal_plc_send_wrrd_cmd;
x_atpl360_hal_wrp.plc_enable_int = hal_plc_enable_interrupt;
x_atpl360_hal_wrp.plc_delay = hal_plc_delay;
atpl360_init(&sx_atpl360_desc, &x_atpl360_hal_wrp);
/* Callback configuration. Set NULL as Not used */
x_atpl360_cbs.data_confirm = NULL;
x_atpl360_cbs.data_indication = NULL;
x_atpl360_cbs.exception_event = NULL;
x_atpl360_cbs.addons_event = _handler_serial_atpl360_event;
x_atpl360_cbs.sleep_mode_cb = _handler_sleep_mode_resume_event;
x_atpl360_cbs.debug_mode_cb = NULL;
sx_atpl360_desc.set_callbacks(&x_atpl360_cbs);
/* Enable ATPL360 */
uc_ret = atpl360_enable(ATPL360_BINARY_ADDRESS, ATPL360_BINARY_LEN);
if (uc_ret == ATPL360_ERROR) {
printf("\r\nmain: atpl360_enable call error!(%d)\r\n", uc_ret);
while (1) {
}
}
while (1) {
/* Check ATPL360 pending events */
atpl360_handle_events();
}
}
PL360
Initialization Example
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 15
5. Configuration
The PL360 firmware has a set of configurable parameters that control its behavior. There is a set of configuration
APIs provided to the host MCU application to configure these parameters. The configuration APIs are categorized
according to their functionality: application, coupling parameters and secure mode.
Any parameter left unset by the host MCU application will use the default value assigned during the initialization of
the PL360 firmware.
Info: All configuration parameters described in this chapter can be found in file.conf_atpl360.h
5.1 Configure Application
The following parameters can be modified in the file to alter the behavior of the device.conf_atpl360.h
• : Use add-on capabilitiesATPL360_ADDONS_ENABLE
– Serial Interface: provides handling of messages to communicate with the Microchip PLC PHY Tester PC
tool and PLC Python scripts
– Sniffer Interface: provides handling of messages to communicate with the Microchip PLC Sniffer PC tool
Info: These add-on modules are included in the PLC PHY workspace provided by Microchip. This
workspace contains the projects to use with the Microchip PLC tools commented previously.
• : Only in case of G3 communication stack, the frequency band can be selected depending onATPL360_WB
customer requirements. G3 CENELEC-A, CENELEC-B, FCC and ARIB bands are available. Take into account
that this configuration requires the use of different firmware binary files in the PL360 device. For further
information, please refer to .12.2.1 Bandplan Selection
5.2 Configure Secure Mode
For information about configuration of the Secure mode, please consult the PL360 Security Features document.
PL360
Configuration
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 16
6. Host Interface Management
The PL360 Host Controller services are divided in two categories: synchronous and asynchronous services. Please
refer to section .4.4 PLC Event Handling
Most of the services implemented by the PL360 Host Controller are asynchronous.
The synchronous service is only used in the function in order to get specific internal parameters relativeget_config
to the communication stack.
When a function from the API is called, a sequence of actions is activated to format the request and to arrange to
transfer it to the PL360 device through the SPI protocol.
When an asynchronous event occurs, the PL360 Host Controller handles the PLC interrupt, checks the events
reported by the PL360 device and extracts the information relative to the notified event.
The associated callback will be invoked in the next call to function.atpl360_handle_events
6.1 Message Transmission
The following figure shows the steps involved in the transmission of a message from the PL360 Host Controller to the
PL360 device.
Figure 6-1. Sequence of Message Transmission
6.2 Message Reception
The following figure shows the steps involved in the reception of a message from the PL360 device to the PL360
Host Controller.
Figure 6-2. Sequence of Message Reception
PL360
Host Interface Management
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 17
The flags field contains information about the reset type of the last reset event:
• USER_RST: User reset
• CM7_RST: Cortex reset
• WDG_RST: Watchdog reset
Table 7-1. Boot Signature Data
31 30 29 28 27 26 25 24
0 1 0 1 0 1 1 0
23 22 21 20 19 18 17 16
0 0 1 1 0 1 0 USER_RST
15 14 13 12 11 10 9 8
CM7_RST WDG_RST – – – – – –
7 6 5 4 3 2 1 0
– – – – – – – –
7.3 Firmware Command Format
The following frame format is used for firmware commands, where the PL360 device supports an address of two
bytes.
Figure 7-2. Firmware Command Fields
The address field contains the identification number of the region to access data. These region numbers are
described in section .7.5 Firmware Data Memory Regions
The CMD field (1 bit), which is the most significant bit of the length field, contains the SPI command:
• Read command: 0
• Write command: 1
The length field (15 bits) contains the number of 16-bit blocks to read.
The payload field depends on the region number to access and on the communication stack in use, G3 or PRIME.
For further information, please refer to file.atpl360_comm.h
7.4 Firmware Response Format
The following frame format is used for firmware responses.
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 19
Figure 7-3. Firmware Response Fields
The header field contains the firmware signature data (0x1122). This field is fixed by the PL360 embedded firmware
and is used to check if this firmware runs properly.
Info: Due to the 16-bit configuration used in this SPI firmware transaction, the firmware signature is
stored in memory as 0x2211.
The payload field depends on the PLC communication stack in use (G3 or PRIME). For further information, please
refer to file.atpl360_comm.h
7.5 Firmware Data Memory Regions
This section shows the data memory regions defined in the PL360 device depending on which PLC communication
stack is used.
The only difference between PRIME and G3 communication stacks regarding data memory regions is the number of
transmission messages that can be simultaneously queued. In case of G3, only one message can be queued. In
case of PRIME, two transmission messages can be queued simultaneously. This is possible because there are two
transmission buffers defined in the PRIME PL360 embedded firmware, TX0 and TX1.
CAUTION
In both cases, G3 and PRIME, upper layers are responsible for managing multiple TX times in order to
avoid collisions between them.
7.5.1 G3 Memory Regions
The following table defines memory regions to use with the G3 communication stack:
Table 7-2. G3 Memory Regions Table
Region Name Value Comments
ATPL360_STATUS_INFO_ID 0 Information relative to the system timer and system events
occurrences in the PL360 firmware
ATPL360_TX_PARAM_ID 1 Information relative to parameters of the last transmission
ATPL360_TX_DATA_ID 2 Information relative to data of the last transmission
ATPL360_TX_CFM_ID 3 Information relative to the confirmation of the last transmission
ATPL360_RX_PARAM_ID 4 Information relative to parameters of the last received message
ATPL360_RX_DATA_ID 5 Information relative to data of the last received message
ATPL360_REG_INFO_ID 6 Information relative to internal registers or PIB’s
7.5.2 PRIME Memory Regions
The following table defines memory regions to use with the PRIME communication stack:
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 20
Figure 7-4. G3 Send Message SPI Sequence
7.6.1.1 G3: Send Parameters
Figure 7-5. G3 Send Parameters SPI Array
In a transmission of parameters, the following can be seen:
• Master (MOSI):
– Send ID memory region(16 bits): 0x0001 ( )ATPL360_TX_PARAM_ID
– Send SPI command (1 bit): 1 (write command)
– Send SPI params length (15 bits) (in blocks of 16-bits): 0x14 (40 bytes)
– Send configuration parameters of G3 transmission (40 bytes) [example in CEN-A band]
• Slave (MISO): PL360 device responds with the Firmware Header (0x1122)
• IRQ is not used in this request operation
7.6.1.2 G3: Send Data
Figure 7-6. G3 Send Data SPI Array
In a transmission of data, the following can be seen:
• Master (MOSI):
– Send ID memory region(16 bits): 0x0002 ( )ATPL360_TX_DATA_ID
– Send SPI command (1 bit): 1 (write command)
– Send SPI data length (15 bits) (in blocks of 16-bits): 0x04 (8 bytes)
– Send data of G3 transmission (8 bytes)
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 22
• Slave (MISO): PL360 device responds with the Firmware Header (0x1122)
• IRQ is not used in this request operation
7.6.2 G3: Read TX confirm Information
When message transmission is complete, the PL360 device reports the status of the last transmission. For that
purpose, IRQ is used to notify the PL360 Host Controller that an event has occurred.
Figure 7-7. G3 Read TX Confirm SPI Sequence
In the figure above, the following can be seen:
• IRQ is used to notify of PL360 events
• First SPI transaction corresponds to the retrieval of event information from the PL360 device
• Second SPI transaction corresponds to the retrieval of confirmation data from the PL360 device (if needed)
7.6.2.1 Get Events Information
Figure 7-8. G3 Get Events Information SPI Array
In the retrieval of event information, the following can be seen:
• Master (MOSI):
– Send ID memory region(16 bits): 0x0000 ( )ATPL360_STATUS_INFO_ID
– Send SPI command (1 bit): 0 (read command)
– Send SPI data length (15 bits) (in blocks of 16 bits): 0x04 (8 bytes)
• Slave (MISO):
– Send Firmware Header (16 bits): 0x1122
– Send Firmware Events (16 bits): 0x0001 ( )ATPL360_TX_CFM_FLAG_MASK
– Send Firmware Timer reference (32 bits)
– Send Firmware Events Information (32 bits). Only valid in case of data indication
( ) or register response ( ) events. It isATPL360_RX_DATA_IND_FLAG_MASK ATPL360_REG_RSP_MASK
used to report the length of the data to be read
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 23
7.6.2.2 Get Confirmation Data
Figure 7-9. G3 Get Confirmation Data SPI Array
If there is a pending event, it is needed to read information relative to the TXATPL360_TX_CFM_FLAG_MASK
confirmation event:
• Master (MOSI):
– Send ID memory region(16 bits): 0x0003 ( )ATPL360_TX_CFM_ID
– Send SPI command (1 bit): 0 (read command)
– Send SPI data length (15 bits) (in blocks of 16-bits): 0x05 (10 bytes)
• Slave (MISO):
– Send Firmware Header (16 bits): 0x1122
– Send Firmware Events (16 bits): 0x0001 ( )ATPL360_TX_CFM_FLAG_MASK
– Send Firmware TX confirmation data:
• RMS calc value (32 bits)
• Transmission Time (32 bits)
• Transmission Result (8 bits)
If there are no pending events to attend, the nterrupt line is disabled.
7.6.3 G3: Receive Message
Figure 7-10. G3 Receive Message SPI Sequence
Message reception is composed of four SPI transactions in two interruption blocks:
• IRQ 1: Get data part of the message (two transactions):
– Get Events Information
– Get Data
• IRQ 2: Get parameters part of the message (two transactions):
– Get Events Information
– Get Parameters
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 24
7.6.3.1 Get Events Information and Data
Figure 7-11. G3 Get Events Information and Data SPI Arrays
If IRQ occurs (enabled in low), it is first needed to read events reported by the PL360 device.
• Master (MOSI):
– Send ID memory region(16 bits): 0x0000 ( )ATPL360_STATUS_INFO_ID
– Send SPI command (1 bit): 0 (read command)
– Send SPI data length (15 bits) (in blocks of 16-bits): 0x04 (8 bytes)
• Slave (MISO):
– Send Firmware Header (16 bits): 0x1122
– Send Firmware Events (16 bits): 0x0002 ( )ATPL360_RX_DATA_IND_FLAG_MASK
– Send Firmware Timer reference (32 bits)
– Send Firmware Events Information (32 bits)
• First 16 bits: Not valid
• Second 16 bits: Length of the data to be read in next transaction (D_LEN)
The next transaction gets the data part of the message:
• Master (MOSI):
– Send ID memory region(16 bits): 0x0005 ( )ATPL360_RX_DATA_ID
– Send SPI command (1 bit): 0 (read command)
– Send SPI data length (15 bits) (in blocks of 16-bits): Use (D_LEN/2) obtained in previous transaction
• Slave (MISO):
– Send Firmware Header (16 bits): 0x1122
– Send Firmware Events (16 bits): 0x0002 ( )ATPL360_RX_DATA_IND_FLAG_MASK
– Send Firmware RX data (variable)
7.6.3.2 Get Events Information and Parameters
Figure 7-12. G3 Get Events Information and Parameters SPI Arrays
If IRQ occurs (enabled in low), first it is needed to read events reported by the PL360 device.
• Master (MOSI):
– Send ID memory region(16 bits): 0x0000 ( )ATPL360_STATUS_INFO_ID
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 25
– Send SPI command (1 bit): 0 (read command)
– Send SPI data length (15 bits) (in blocks of 16-bits): 0x04 (8 bytes)
• Slave (MISO):
– Send Firmware Header (16 bits): 0x1122
– Send Firmware Events (16 bits): 0x0010 ( )ATPL360_RX_QPAR_IND_FLAG_MASK
– Send Firmware Timer reference (32 bits)
– Send Firmware Events Information (32 bits): Not valid
The next transaction gets the parameters part of the message:
• Master (MOSI):
– Send ID memory region(16 bits): 0x0004 ( )ATPL360_RX_PARAM_ID
– Send SPI command (1 bit): 0 (read command)
– Send SPI data length (15 bits) (in blocks of 16-bits): Variable length depending on G3 band
• Slave (MISO):
– Send Firmware Header (16 bits): 0x1122
– Send Firmware Events (16 bits): 0x0010 ( )ATPL360_RX_QPAR_IND_FLAG_MASK
– Send Firmware RX parameters. See rx_msg_t structure in fileatpl360_comm.h
7.6.4 PRIME: Send Message (Buffer 0)
In a message transmission, there is only one SPI transaction that includes both parameters and data.
Figure 7-13. PRIME Send Message SPI Array
In the figure above, the following can be seen:
• Master (MOSI):
– Send ID memory region(16 bits): 0x0001 ( )ATPL360_TX0_PARAM_ID
– Send SPI command (1 bit): 1 (write command)
– Send SPI params length (15 bits) (in blocks of 16-bits): (param length + data length) / 2, where param
length is 12 bytes
– Send configuration parameters of PRIME transmission (12 bytes)
– Send data part of message (variable)
• Slave (MISO): PL360 responds with Firmware Header (0x1122)
IRQ is not used in this request operation.
7.6.5 PRIME: Read TX confirm Information (Buffer 0)
When message transmission is complete, the PL360 device reports the status of the last transmission. For that
purpose, IRQ is used to notify the PL360 Host Controller that an event has occurred.
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 26
Figure 7-14. PRIME TX Confirm Information SPI Sequence
In the figure above, the following can be seen:
• IRQ is used to notify of PL360 events
• First SPI transaction corresponds to the retrieval of event information from the PL360 device
• Second SPI transaction corresponds to the retrieval of confirmation data from the PL360 device (if needed)
7.6.5.1 Get Events Information (Buffer 0)
Figure 7-15. PRIME Events Information SPI Array
It is similar to the flow described in section , but changing the firmware descriptors for7.6.2.1 Get Events Information
the ones applicable to the PRIME PL360 firmware.
7.6.5.2 Get Confirmation Data (Buffer 0)
Figure 7-16. PRIME Confirmation Data SPI Array
It is similar to the flow described in section , but changing the firmware descriptors for7.6.2.2 Get Confirmation Data
the ones applicable to the PRIME PL360 firmware.
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 27
7.6.6.3 Get Parameters Information
Figure 7-20. PRIME Get Parameters SPI Array
It is similar to the flow described in section , but changing the7.6.3.2 Get Events Information and Parameters
firmware descriptors for the ones applicable to the PRIME PL360 firmware.
7.6.7 Read Register Information
It is possible to get internal information from the PL360 device.
Figure 7-21. Read Register Information SPI Sequence
In the figure above, three SPI transactions can be seen:
• Request register information
• Get events information
• Get register value
7.6.7.1 Request Register Information
Figure 7-22. Request Register Information Array
• Master (MOSI):
– Send ID memory region(16 bits): 0x0006 ( ) [example with G3]ATPL360_REG_INFO_ID
– Send SPI command (1 bit): 1 (write command)
– Send SPI params length (15 bits) (in blocks of 16-bits): 0x0004 (8 bytes)
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 29
– Send register identification (4 bytes). See section or 12.2.5 PIB Objects Specification and Access (G3)
12.3.4 PIB Objects Specification and Access (PRIME)
– Send length of the register to read (2 bytes)
• Slave (MISO): PL360 device responds with firmware header (0x1122)
7.6.7.2 Get Events Information
Figure 7-23. Get Events Information Array
• Master (MOSI):
– Send ID memory region(16 bits): 0x0000 ( )ATPL360_STATUS_INFO_ID
– Send SPI command (1 bit): 0 (read command)
– Send SPI data length (15 bits) (in blocks of 16 bits): 0x04 (8 bytes)
• Slave (MISO):
– Send Firmware Header (16 bits): 0x1122
– Send Firmware Events (16 bits): 0x0008 ( )ATPL360_REG_RSP_MASK
– Send Firmware Timer reference (32 bits)
– Send Firmware Events Information (32 bits)
• First 16 bits: Length of the register value to read in next transaction. (D_REG)
• Second 16 bits: Not valid
7.6.7.3 Get Register Value
Figure 7-24. Get Register Value SPI Array
• Master (MOSI):
– Send ID memory region(16 bits): 0x0006 ( )ATPL360_REG_INFO_ID
– Send SPI command (1 bit): 0 (read command)
– Send SPI data length (15 bits) (in blocks of 16 bits): Variable length depending on register to read (D_REG)
• Slave (MISO):
– Send Firmware Header (16 bits): 0x1122
– Send Firmware Events (16 bits): 0x008 ( )ATPL360_REG_RSP_MASK
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 30
– Send Firmware register value. See section or 12.2.5 PIB Objects Specification and Access (G3) 12.3.4
PIB Objects Specification and Access (PRIME)
PL360
SPI Protocol
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 31
8. Example Applications
CAUTION
Please note that all the provided application examples have been configured to work on Microchip
evaluation boards. When using other hardware, the firmware project must define a Board Support
Package (BSP) customized for that hardware.
Along with the PLC communication stacks, specific application examples are provided in order to show how to
integrate the PL360 Host Controller.
In addition, PHY examples using only the PL360 Host Controller are provided in order to evaluate some low level
parameters and to be used together with a Microchip PLC tool for demonstration purposes.
In case of a G3 stack, applications are provided for CENELEC A, CENELEC B and FCC bands (project folders with
suffixes “_cen_a”, “_cen_b” and “_fcc” in each example). Setting the appropriate band in each project is made by
means of , as explained in section .conf_atpl360.h file 5.1 Configure Application
In case of a PRIME stack, applications are provided for CENELEC A and FCC bands (the same project folder is used
in both bands depending on PRIME configured channel. See 12.3.4.30 ATPL360_REG_CHANNEL_CFG (0x4016)).
8.1 PHY Examples
8.1.1 PHY Tester
The PHY Tester is an application example that demonstrates the complete performance of the Microchip PLC PHY
layer. This example requires a board and a PC tool. In addition, the Microchip PLC PHY Tester PC tool (available in
the Microchip website) has to be installed on the user’s host PC to interface with the boards.
The Microchip PLC PHY Tester PC tool configures the devices and performs communication tests.
This example uses the serial interface configured through UART0 at 230400bps.
8.1.2 PHY Sniffer
The PHY Sniffer is an application example to monitor data traffic in the PLC network and then send it via serial
communications to a PC tool and the Microchip PLC Sniffer PC tool (available in the Microchip website), which has to
be installed in the user’s host PC to interface with the board. This example requires only one board and (obviously) a
PLC network to be monitored.
This example uses the serial interface configured through UART0 at 230400bps.
8.1.3 TX Console
Due to PC timing, the Microchip PLC PHY Tester PC tool may present limitations in those applications or tests that
require a very short time interval between consecutive frame transmissions.
The PHY TX Console is an application example that demonstrates the complete performance of the Microchip PLC
PHY Layer avoiding the limitations of timing in the PC host. This way, users can perform more specific PHY tests
(e.g., short time interval between consecutive frames).
This application offers an interface to the user by means of a command console. In this console, users can configure
several transmission parameters such as modulation, frame data length and time interval between frames. In the
console it is also possible to test transmission/reception processes.
This example uses the serial interface configured through UART0 at 921600bps.
8.1.4 PHY Getting Started
This example is intended to show the minimal application to be developed over the PL360 PHY layer (G3 or PRIME).
Two modes of operation can be configured: or . The former will startCONF_APP_TX_MODE CONF_APP_RX_MODE
sending PHY frames without user intervention, while the latter will wait for frame receptions from the PHY layer. Both
modes print messages on a Serial Console to inform the user about frames transmitted and received, respectively.
PL360
Example Applications
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 32
Thus, depending on G3 or PRIME PHY layer, the following configuration is allowed:
• G3 ( file):conf_project.h
– : or CONF_APP_MODE CONF_APP_TX_MODE CONF_APP_RX_MODE
– ( ): Time delay between transmitted frames in microsecondsTX_DELAY_US phy_getting_started.c
• PRIME ( file):conf_app_example.h
– : or CONF_APP_MODE CONF_APP_TX_MODE CONF_APP_RX_MODE
– : PRIME channel for transmission and reception (see CONF_PRIME_CHANNEL 12.3.4.30
ATPL360_REG_CHANNEL_CFG (0x4016))
– : Time delay between transmitted frames in microsecondsCONF_TX_DELAY_US
PL360
Example Applications
© 2020 Microchip Technology Inc. User Guide DS50002738E-page 33
Produkt Specifikationer
| Mærke: | Microchip |
| Kategori: | Ikke kategoriseret |
| Model: | PL360B |
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