Microchip AVR128DA32 Manual (166 Sider)

AVR® Instruction Set Manual

Introduction

This manual gives an overview and explanation of every instruction available for 8-bit AVR

® devices. Each instruction

has its own section containing functional description, it’s opcode, and syntax, the end state of the status register, and

cycle times.

The manual also contains an explanation of the different addressing modes used by AVR devices and an appendix

listing all modern AVR devices and what instruction it has available.

Table of Contents

Introduction.....................................................................................................................................................1

1. Instruction Set Nomenclature..................................................................................................................6

2. CPU Registers Located in the I/O Space................................................................................................8

2.1. RAMPX, RAMPY, and RAMPZ.....................................................................................................8

2.2. RAMPD........................................................................................................................................ 8

2.3. EIND.............................................................................................................................................8

3. The Program and Data Addressing Modes.............................................................................................9

3.1. Register Direct, Single Register Rd..............................................................................................9

3.2. Register Direct - Two Registers, Rd and Rr................................................................................. 9

3.3. I/O Direct.................................................................................................................................... 10

3.4. Data Direct................................................................................................................................. 10

3.5. Data Indirect............................................................................................................................... 11

3.6. Data Indirect with Pre-decrement............................................................................................... 11

3.7. Data Indirect with Post-increment.............................................................................................. 12

3.8. Data Indirect with Displacement.................................................................................................12

3.9. Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions............. 13

3.10. Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction................. 13

3.11. Store Program Memory Post-increment.....................................................................................14

3.12. Direct Program Addressing, JMP and CALL.............................................................................. 14

3.13. Indirect Program Addressing, IJMP and ICALL..........................................................................15

3.14. Extended Indirect Program Addressing, EIJMP and EICALL.....................................................15

3.15. Relative Program Addressing, RJMP and RCALL..................................................................... 16

4. Conditional Branch Summary............................................................................................................... 17

5. Instruction Set Summary.......................................................................................................................18

6. Instruction Description...........................................................................................................................24

6.1. ADC – Add with Carry................................................................................................................ 24

6.2. ADD – Add without Carry........................................................................................................... 25

6.3. ADIW – Add Immediate to Word................................................................................................ 26

6.4. AND – Logical AND....................................................................................................................27

6.5. ANDI – Logical AND with Immediate..........................................................................................28

6.6. ASR – Arithmetic Shift Right...................................................................................................... 29

6.7. BCLR – Bit Clear in SREG......................................................................................................... 30

6.8. BLD – Bit Load from the T Bit in SREG to a Bit in Register....................................................... 31

6.9. BRBC – Branch if Bit in SREG is Cleared..................................................................................32

6.10. BRBS – Branch if Bit in SREG is Set......................................................................................... 33

6.11. BRCC – Branch if Carry Cleared................................................................................................34

6.12. BRCS – Branch if Carry Set....................................................................................................... 35

6.13. BREAK – Break..........................................................................................................................36

6.14. BREQ – Branch if Equal.............................................................................................................36

6.15. BRGE – Branch if Greater or Equal (Signed).............................................................................37

6.16. BRHC – Branch if Half Carry Flag is Cleared.............................................................................38

AVR® Instruction Set Manual

6.65. LAT – Load and Toggle.............................................................................................................. 86

6.66. LD – Load Indirect from Data Space to Register using X...........................................................87

6.67. LD (LDD) – Load Indirect from Data Space to Register using Y................................................ 89

6.68. LD (LDD) – Load Indirect From Data Space to Register using Z............................................... 90

6.69. LDI – Load Immediate................................................................................................................ 92

6.70. LDS – Load Direct from Data Space.......................................................................................... 93

6.71. LDS (AVRrc) – Load Direct from Data Space............................................................................ 94

6.72. LPM – Load Program Memory................................................................................................... 95

6.73. LSL – Logical Shift Left.............................................................................................................. 96

6.74. LSR – Logical Shift Right........................................................................................................... 97

6.75. MOV – Copy Register................................................................................................................ 98

6.76. MOVW – Copy Register Word................................................................................................... 99

6.77. MUL – Multiply Unsigned......................................................................................................... 100

6.78. MULS – Multiply Signed........................................................................................................... 101

6.79. MULSU – Multiply Signed with Unsigned.................................................................................102

6.80. NEG – Two’s Complement....................................................................................................... 103

6.81. NOP – No Operation................................................................................................................ 104

6.82. OR – Logical OR...................................................................................................................... 105

6.83. ORI – Logical OR with Immediate............................................................................................106

6.84. OUT – Store Register to I/O Location...................................................................................... 107

6.85. POP – Pop Register from Stack...............................................................................................108

6.86. PUSH – Push Register on Stack..............................................................................................109

6.87. RCALL – Relative Call to Subroutine....................................................................................... 110

6.88. RET – Return from Subroutine................................................................................................. 111

6.89. RETI – Return from Interrupt.................................................................................................... 112

6.90. RJMP – Relative Jump............................................................................................................. 113

6.91. ROL – Rotate Left trough Carry................................................................................................114

6.92. ROR – Rotate Right through Carry...........................................................................................115

6.93. SBC – Subtract with Carry........................................................................................................116

6.94. SBCI – Subtract Immediate with Carry SBI – Set Bit in I/O Register....................................... 117

6.95. SBI – Set Bit in I/O Register..................................................................................................... 118

6.96. SBIC – Skip if Bit in I/O Register is Cleared............................................................................. 119

6.97. SBIS – Skip if Bit in I/O Register is Set.................................................................................... 120

6.98. SBIW – Subtract Immediate from Word................................................................................... 121

6.99. SBR – Set Bits in Register....................................................................................................... 122

6.100. SBRC – Skip if Bit in Register is Cleared.................................................................................123

6.101. SBRS – Skip if Bit in Register is Set........................................................................................ 124

6.102. SEC – Set Carry Flag...............................................................................................................125

6.103. SEH – Set Half Carry Flag....................................................................................................... 126

6.104. SEI – Set Global Interrupt Enable Bit.......................................................................................127

6.105. SEN – Set Negative Flag......................................................................................................... 128

6.106. SER – Set all Bits in Register...................................................................................................128

6.107. SES – Set Sign Flag................................................................................................................ 129

6.108. SET – Set T Bit........................................................................................................................ 130

6.109. SEV – Set Overflow Flag......................................................................................................... 131

6.110. SEZ – Set Zero Flag.................................................................................................................132

6.111. SLEEP......................................................................................................................................132

6.112. SPM (AVRe) – Store Program Memory....................................................................................133

AVR® Instruction Set Manual

6.113. SPM (AVRxm, AVRxt) – Store Program Memory.....................................................................135

6.114. ST – Store Indirect From Register to Data Space using Index X.............................................136

6.115. ST (STD) – Store Indirect From Register to Data Space using Index Y.................................. 138

6.116. ST (STD) – Store Indirect From Register to Data Space using Index Z...................................140

6.117. STS – Store Direct to Data Space............................................................................................141

6.118. STS (AVRrc) – Store Direct to Data Space.............................................................................. 142

6.119. SUB – Subtract Without Carry..................................................................................................143

6.120. SUBI – Subtract Immediate......................................................................................................144

6.121. SWAP – Swap Nibbles.............................................................................................................145

6.122. TST – Test for Zero or Minus................................................................................................... 146

6.123. WDR – Watchdog Reset.......................................................................................................... 147

6.124. XCH – Exchange......................................................................................................................148

7. Appendix A Device Core Overview..................................................................................................... 149

7.1. Core Descriptions.....................................................................................................................149

7.2. Device Tables...........................................................................................................................150

8. Revision History.................................................................................................................................. 161

8.1. Rev. DS40002198B - 02/2021..................................................................................................161

8.2. Rev. DS40002198A - 05/2020..................................................................................................161

8.3. Rev.0856L - 11/2016................................................................................................................ 161

8.4. Rev.0856K - 04/2016................................................................................................................161

8.5. Rev.0856J - 07/2014................................................................................................................ 161

8.6. Rev.0856I – 07/2010................................................................................................................ 161

8.7. Rev.0856H – 04/2009...............................................................................................................162

8.8. Rev.0856G – 07/2008.............................................................................................................. 162

8.9. Rev.0856F – 05/2008...............................................................................................................162

The Microchip Website...............................................................................................................................163

Product Change Notification Service..........................................................................................................163

Customer Support...................................................................................................................................... 163

Microchip Devices Code Protection Feature..............................................................................................163

Legal Notice............................................................................................................................................... 164

Trademarks................................................................................................................................................ 164

Quality Management System..................................................................................................................... 165

Worldwide Sales and Service.....................................................................................................................166

AVR® Instruction Set Manual

3.11 Store Program Memory Post-increment

Figure 3-11. Store Program Memory

Z - POINTER

2

The Z-pointer is incremented by 2 after the operation. Constant byte address is specified by the Z-pointer contents

before incrementing. The 15 MSbs select word address and the LSb should be left cleared.

3.12 Direct Program Addressing, JMP and CALL

Figure 3-12. Direct Program Memory Addressing

OP

PC

k

Program execution continues at the address immediate in the instruction word.

AVR® Instruction Set Manual

The Program and Data Addressing Modes

...........continued

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

LD Rd, Y Load Indirect Rd ← DS(Y) None 2

(1) 2(1)(3) 2(2) 1 / 2

LD Rd, Y+ Load Indirect and Post-Increment Rd

Y

←

DS(Y)

Y + 1

None 2(1) 2(1)(3) 2(2) 2 / 3

LD Rd, -Y Load Indirect and Pre-Decrement Y

Rd

←

Y - 1

DS(Y)

None 2(1) 3(1)(3) 2(2) 2 / 3

LDD Rd, Y+q Load Indirect with Displacement Rd ← DS(Y + q) None 2

(1) 3(1)(3) 2(2) N/A

LD Rd, Z Load Indirect Rd ← DS(Z) None 2

(1) 2(1)(3) 2(2) 1 / 2

LD Rd, Z+ Load Indirect and Post-Increment Rd

Z

←

DS(Z)

Z+1

None 2(1) 2(1)(3) 2(2) 2 / 3

LD Rd, -Z Load Indirect and Pre-Decrement Z

Rd

←

Z - 1

DS(Z)

None 2(1) 3(1)(3) 2(2) 2 / 3

LDD Rd, Z+q Load Indirect with Displacement Rd ← DS(Z + q) None 2

(1) 3(1)(3) 2(2) N/A

STS k, Rr Store Direct to Data Space DS(k) ← Rd None 2

(1) 2(1) 2(2) 1

ST X, Rr Store Indirect DS(X) ← Rr None 2

(1) 1(1) 1(2) 1

ST X+, Rr Store Indirect and Post-Increment DS(X)

X

←

Rr

X + 1

None 2(1) 1(1) 1(2) 1

ST -X, Rr Store Indirect and Pre-Decrement X

DS(X)

←

X - 1

Rr

None 2(1) 2(1) 1(2) 2

ST Y, Rr Store Indirect DS(Y) ← Rr None 2

(1) 1(1) 1(2) 1

ST Y+, Rr Store Indirect and Post-Increment DS(Y)

Y

←

Rr

Y + 1

None 2(1) 1(1) 1(2) 1

ST -Y, Rr Store Indirect and Pre-Decrement Y

DS(Y)

←

Y - 1

Rr

None 2(1) 2(1) 1(2) 2

STD Y+q, Rr Store Indirect with Displacement DS(Y + q) ← Rr None 2

(1) 2(1) 1(2) N/A

ST Z, Rr Store Indirect DS(Z) ← Rr None 2

(1) 1(1) 1(2) 1

ST Z+, Rr Store Indirect and Post-Increment DS(Z)

Z

←

Rr

Z + 1

None 2(1) 1(1) 1(2) 1

ST -Z, Rr Store Indirect and Pre-Decrement Z

DS(Z)

←

Z - 1

Rr

None 2(1) 2(1) 1(2) 2

STD Z+q,Rr Store Indirect with Displacement DS(Z + q) ← Rr None 2

(1) 2(1) 1(2) N/A

LPM Load Program Memory R0 ← PS(Z) None 3 3 3 N/A

LPM Rd, Z Load Program Memory Rd ← PS(Z) None 3 3 3 N/A

LPM Rd, Z+ Load Program Memory and Post-

Increment

Rd

Z

←

PS(Z)

Z + 1

None 3 3 3 N/A

ELPM Extended Load Program Memory R0 ← PS(RAMPZ:Z) None 3 3 3 N/A

ELPM Rd, Z Extended Load Program Memory Rd ← PS(RAMPZ:Z) None 3 3 3 N/A

ELPM Rd, Z+ Extended Load Program Memory

and Post-Increment

Rd

(RAMPZ:Z)

←

PS(RAMPZ:Z)

(RAMPZ:Z) + 1

None 3 3 3 N/A

SPM Store Program Memory PS(RAMPZ:Z) ← R1:R0 None -(4) -(4) -(4) N/A

SPM Z+ Store Program Memory and Post-

Increment by 2

PS(RAMPZ:Z)

Z

←

R1:R0

Z + 2

None N/A - (4) -(4) N/A

AVR® Instruction Set Manual

Instruction Set Summary

Table 6-1. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.2 ADD – Add without Carry

6.2.1 Description

Adds two registers without the C flag and places the result in the destination register Rd.

Operation:

(i) (i) Rd ← Rd + Rr

Syntax: Operands: Program Counter:

(i) ADD Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0000 11rd dddd rrrr

6.2.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

H Rd3 Rr3 Rr3 R3 R3 Rd3∧ ∨ ∧ ∨ ∧

Set if there was a carry from bit 3; cleared otherwise.

S N V, for signed tests.⊕

V Rd7 Rr7 R7 Rd7 Rr7 R7∧ ∧ ∨ ∧ ∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

C Rd7 Rr7 Rr7 R7 R7 Rd7∧ ∨ ∧ ∨ ∧

Set if there was a carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

AVR® Instruction Set Manual

Instruction Description

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Model:	AVR128DA32

Microchip AVR128DA32 Manual

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