Microchip dsPIC33CK512MP305 Manual
Microchip
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dsPIC33CK512MP305
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HRPWM with Fine Edge
Placement
dsPIC33/PIC24 Family Reference Manual
Introduction
Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on
the device variant, this manual section may not apply to all dsPIC33 devices. Please consult the note at the
beginning of the chapter in the specific device data sheet to check whether this document supports the device you
are using.
Device data sheets and family reference manual sections are available for download from the Microchip Worldwide
Website at: www.microchip.com.
This document describes the features and use of the High-Resolution Pulse-Width Modulated (PWM) with Fine Edge
Placement. This flexible module provides features to support many types of Motor Control (MC) and Power Control
(PC) applications, including:
• AC-to-DC Converters
• DC-to-DC Converters
• AC and DC Motor Control: Brushed DC, BLDC, PMSM, ACIM, SRM, Stepper, etc.
• Inverters
• Battery Chargers
• Digital Lighting
• Power Factor Correction (PFC)
High-Level Features
• Up to Eight Independent PWM Generators, each with Dual Outputs
• Operating modes:
– Independent Edge PWM mode
– Variable Phase PWM mode
– Independent Edge PWM mode, Dual Output
– Center-Aligned PWM mode
– Double Update Center-Aligned PWM mode
– Dual Edge Center-Aligned PWM mode
• Output modes:
– Complementary
– Independent
– Push-Pull
• Dead-Time Generator
• Dead-Time Compensation
• Leading-Edge Blanking (LEB)
• Output Override for Fault Handling
• Flexible Period/Duty Cycle Updating Options
• PWM Control Inputs (PCI) for PWM Pin Overrides and External PWM Synchronization
• Advanced Triggering Options
• Combinatorial Logic Output
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 1
• PWM Event Outputs
HRPWM with Fine Edge Placement
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 2
2.1 Common Functions Register Map
Note: The number of LOGCONy and PWMEVTy registers are device-dependent. Refer to the device data sheet for
availability.
Name Bit Pos. 7 6 5 4 3 2 1 0
PCLKCON 7:0 DIVSEL[1:0] MCLKSEL[1:0]
15:8 HRRDY HRERR LOCK
FSCL 7:0 FSCL[7:0]
15:8 FSCL[15:8]
FSMINPER 7:0 FSMINPER[7:0]
15:8 FSMINPER[15:8]
MPHASE 7:0 MPHASE[7:0]
15:8 MPHASE[15:8]
MDC 7:0 MDC[7:0]
15:8 MDC[15:8]
MPER 7:0 MPER[7:0]
15:8 MPER[15:8]
LFSR 7:0 LFSR[7:0]
15:8 LFSR[14:8]
CMBTRIGL 7:0 CTA8EN CTA7EN CTA6EN CTA5EN CTA4EN CTA3EN CTA2EN CTA1EN
15:8
CMBTRIGH 7:0 CTB8EN CTB7EN CTB6EN CTB5EN CTB4EN CTB3EN CTB2EN CTB1EN
15:8
LOGCONy 7:0 S1yPOL S2yPOL PWMLFy[1:0] PWMLFyD[2:0]
15:8 PWMS1y[3:0] PWMS2y[3:0]
PWMEVTy 7:0 EVTySEL[3:0] EVTyPGS[2:0]
15:8 EVTyOEN EVTyPOL EVTySTRD EVTySYNC
HRPWM with Fine Edge Placement
Register Maps
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 7
2.1.3 Frequency Scaling Minimum Period Register
Name: FSMINPER
Bit 15 14 13 12 11 10 9 8
FSMINPER[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FSMINPER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 15:0 – FSMINPER[15:0] Frequency Scaling Minimum Period Register
This register holds the minimum clock period (maximum clock frequency) that can be produced by the frequency
scaling circuit.
HRPWM with Fine Edge Placement
Register Maps
© 2017-2020 Microchip Technology Inc. Functional Reference Manuals (FRM) DS70005320D-page 10
Produkt Specifikationer
| Mærke: | Microchip |
| Kategori: | Ikke kategoriseret |
| Model: | dsPIC33CK512MP305 |
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