MD1213DB1
Doc.# DSDB-MD1213DB1
B032114
MD1213 + TC6320 Demoboard
High Speed ±100V 2A Pulser
General Description
The MD1213DB1 can drive a transducer as a single chan-
nel transmitter for ultrasound and other applications. The
demoboard consists of one MD1213 in a 12-Lead 4x4x0.9mm
QFN (K6) package, combined with Supertex’s TC6320, an
IC containing high voltage P- and N- channel FETs in a 8-
Lead SOIC package.
Logic control inputs INA, INB and OE of the MD1213 are
controlled via the six-pin head connector on the board. Due
to the fast signal rise and fall time requirement, every ground
wire of the ribbon cable must be used to connect from the
logic signal source. When OE is enabled, it should recieve
the same voltage as the logic source circuit’s power supply.
The MD1213DB1 output waveforms can be displayed direct-
ly using an oscilloscope by connecting the scope probe to
the test point TP10-1 and TP10-2 (GND). The J5 jumper can
select whether or not to connect the on-board equivalent-
load, a 220pF 200V capacitor paralleled with a 1.0kΩ, 1W
resistor. Also, a coaxial cable can be used to easily connect
to the user’s transducer.
Demoboard Features
Demonstrates one channel ultrasound transmitter►
MD1213 driving a TC6320 power MOSFET►
±2.0 A source and sink current capability►
Logic control signal input connector ►
SMA connectors for cable to a transducer►
1.8 to 3.3V CMOS logic interface►
Designing a Pulser with the MD1213
Low input capacitance and fast switching speed are the
important features of the MD1213’s input stage. Its logic inputs
have an input impedance of about 20kΩ in parallel with 5pF,
and an internal speed of around 100MHz. The output enable
pin, OE, determines the threshold voltage for the input-channel
level translators. The input stage logic is fully compatible with
1.8V, 2.0V, 2.5V, 3.3V, or 5.0V CMOS logic. The level translators
are also compatible with these logic voltage levels, up to the
MOSFET’s gate-driver voltage level, which is typically 5.0 to
12V. When OE is low, the chip disables its’ outputs, setting
OUTA high and OUTB low. This condition helps to properly pre-
charge the AC coupling capacitors that the user can optionally
add in series with the gate-driver circuit of the external P/N-
channel FET pair.
Block Diagram
OE
INA
INB
HV
OUT
XDCF
R
L
C
L
V
DD
2VH
V
L
INA
OUTA
INB
V
SS
2
VL
OUTB
V
SS
2
Level
Shifter
V
DD
2 V
H
V
SS
1
GND
V
DD
1
1.0µF
0 to 100V
MD1213
TC6320
V
DD
V
H
V
L
OE
V
SS
V
CC
VCC 1.0µF
0 to 100V
