Microchip MIC2297 Manual

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Side 1/8

ANTC204

SY88149NDL and SY88349NDL

Burst Mode Limiting Post Amplifiers

Introduction

This document explains to use the SY88149NDL and SY88349NDL burst mode limiting amplifiers in different how

applications including 1G/10GEPON, XGPON.1, GE- -PON/GPON, Gigabit Ethernet, Fibre Channel, OC 3/12/24

SONET/SDH, and OBSAI/CPRI.

The SY88149NDL (resp. SY88349NDL) is a high sensitivity limiting post amplifier that can am- plify signals as

small as 5mVPP with data rates up to 1.25Gbps (resp. 2.5Gbps). The parts offer LOS or SD outputs depending on

the LOS/SD SEL option. The LOS/SD output can be fed back to JAM input for output stability when there is no the

data present at the input. LOS/SDLVL sets the threshold for the input signal detection.

Both amplifiers offer a fast SD assert (LOS de assert) time of 5ns and a fast SD de assert (LOS assert) time of - -

5ns if manual RESET is used or 120ns if /AUTORESET is used.

Noise Discriminator

The noise discriminator feature is intended for PON OLT applications with gain burst mode TIAs where noise -high -

can trigger a false LOS de assert or SD assert while no input data is present. The noise discriminator will filter -

input data through a series of specialized circuits that will only trigger LOS/SD on the rising edge of a valid PON

1.244Gbps noise (resp. 2.488Gbps) preamble bit stream (10101). The SY88149NDL (resp. SY88349NDL)

discriminator is designed to accept a 1.244 (resp. 2.488 preamble burst. Any Gbps 300 bps± M Gbps 300 bps)± M

other bit pattern will be rejected. If th ed at any other data rate, the noise discriminator should be is part is us

disabled.

The noise discriminator, implemented in the edge detector circuit, can be selected or bypassed by selecting the

proper resistor value using the settings at as shown in the LOS/SDSEL pin, Table 1.

Table 1. Truth Table for SD/LOS Select and Noise Discriminator function

LOS/SDSEL P LOS/SD Sin election N Doise iscriminator I To O nput JAM utputs

0 SD Ωto VCC Enabled HIGH Enabled

0 SD Ωto VCC Enabled LOW Disabled

16k DisabledΩ SD to VCC HIGH Enabled

16k DisabledΩ SD to VCC LOW Disabled

16k DisabledΩ to GND LOS HIGH Disabled

16k DisabledΩ to GND LOS LOW Enabled

0 Ωto GND LOS Enabled HIGH Disabled

0 Ωto GND LOS Enabled LOW Enabled

Micrel Inc. • 2180 Fortune Drive • Jose, CA 95131 • USA • tel +1 (408) 944 0800 • fax + 1 (408) 474 1000 • San - - http://www.micrel.com

April 23, 2014 Revision 1.1

Micrel, Inc.

AN TC204 −SY88149NDL and SY88349NDL Burst Mode Limiting Post Amplifiers

RESET vs. /AUTORESET Operation in Burst Mode Applications

The user can chose to de assert SD (assert LOS) AUTORESET mode or manual RESET. In - using either /

/ - - -AUTORESET mode, the SD de asserts (LOS as er the last highserts) automatically within 120ns aft to low

transition of the input data burst. If the AUTORESET function is disabled, SD must be de/ -asserted (LOS

asserted) manually by applying a RESET pulse at RESET pin.

AC or DC Coupling and Burst Mode Receiver Challenges

The receiver should be able to support data signals with long strings of consecutive identical bits (CID) and power

shift from strong bursts to weak bursts (and vice versa) to avoid getting errors. These two situations won’t be an

issue if the receiver link from the ph to the limiting amplifier to the CDR is DC coupled and otodiode– TIA (ROSA) -

doesn’t contain any coupling capacitors. Unfortunately, DC coupling the limiting amplifier to the TIA requires the -

output of the TIA and the input of the LA to have compatible common mode voltages, and it is unlikely to find a

TIA- LA on the market that satisfies that condition. Therefore, to have more choice in parts selection, the module

designer will more likely use AC coupling between the TIA and LA.

AC-coupling the TIA to the LA comes with some issues the designer should address by using better architecture

and appropriate component values. The two issues that face the use of AC coupling are the presence of long

strings of consecutive identical digits (CID) and receiver threshold settlement time during large power shift s

b etween strong and weak bursts.

CID

CID is defined as consecutive identical digits and may vary from one protocol to another and may be either

consecutive ‘1’ or consecutive ‘0’. It is up to the module designer to ensure that the module will correctly handle

the number of CIDs for the particular application(s).

Figure 1. Eect of CID “1”

Figure 2 . Eect of CID “0”

A small value coupling capacitor will create off frequency (the cap and the termination creates a a higher low-cut-

high- -pass filter) that may cause errors with low frequency data, especially in the presence of long strings of CID.

Additionally, this condition makes the middle of the data eye wander frequency data components. with low-

Therefore, the value of the cap should be large enough to set the low frequency cut off well below the lowest -

frequency component (created by CID) and minimize DC frequency components.level wander with low-

April 23, 2014 2 Revision 1.1

Produkt Specifikationer

Mærke:	Microchip
Kategori:	Ikke kategoriseret
Model:	MIC2297

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