Microchip PIC24F32KA304 Manual

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Side 1/28

CPU

Section 2. CPU

HIGHLIGHTS

This section of the manual contains the following topics:

2.1 Introduction .................................................................................................................... 2-2

2.2 Programmer’s Model...................................................................................................... 2-4

2.3 Software Stack Pointer................................................................................................... 2-7

2.4 CPU Register Descriptions .......................................................................................... 2-10

2.5 Arithmetic Logic Unit (ALU).......................................................................................... 2-13

2.6 Multiplication and Divide Support................................................................................. 2-14

2.7 Compiler Friendly Architecture..................................................................................... 2-17

2.8 Multi-Bit Shift Support .................................................................................................. 2-17

2.9 Instruction Flow Types ................................................................................................. 2-18

2.10 Program Flow Loop Control ......................................................................................... 2-20

2.11 Address Register Dependencies ................................................................................. 2-22

2.12 Register Maps.............................................................................................................. 2-25

2.13 Related Application Notes............................................................................................ 2-26

2.14 Revision History........................................................................................................... 2-27

PIC24F Family Reference Manual

2.1 INTRODUCTION

The PIC24F CPU module has a 16-bit (data) modified Harvard architecture with an enhanced

instruction set. The CPU has a 24-bit instruction word with a variable length opcode field. The

Program Counter (PC) is 24 bits wide and addresses up to 4M x 24 bits of user program memory

space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and

provides predictable execution. All instructions execute in a single cycle, with the exception of

instructions that change the program flow, the double-word move (MOV.D) instruction and the

table instructions. Overhead-free program loop constructs are supported using the REPEAT

instructions, which are interruptible at any point.

The PIC24F devices have sixteen, 16-bit working registers in the programmer’s model. Each of

the working registers can act as a data, address or address offset register. The 16th working

The upper 32 Kbytes of the data space memory map can optionally be mapped into program

space at any 16K word program boundary defined by the 8-bit Program Space Visibility Page

(PSVPAG) register. The data to program space mapping feature lets any instruction access pro-

gram space as if it were data space. Refer to Section 4.4 “Program Space Visibility from Data

Space” for more information on Program Space Visibility.

The Instruction Set Architecture (ISA) is significantly enhanced beyond that of the PIC18F but

maintains an acceptable level of backward compatibility. All PIC18F instructions and addressing

modes are supported either directly or through simple macros. Many of the ISA enhancements

are driven by compiler efficiency needs.

The core supports Inherent (no operand), Relative, Literal and Memory Direct Addressing

modes, and 3 groups of addressing modes (MODE1, MODE2 and MODE3). All modes support

addressing modes. Instructions are associated with predefined addressing modes depending

upon their functional requirements.

There is also a ‘Register Indirect with Signed 10-Bit Offset’ Addressing mode dedicated to two

special move instructions, LDWLO and STWLO. Refer to Section 32. “Instruction Set” for more

details.

For most instructions, the core is capable of executing a data (or program data) memory read, a

working register (data) read, a data memory write and a program (instruction) memory read per

instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C

operations to be executed in a single cycle.

A high-speed, 17-bit by 17-bit multiplier is included to significantly enhance the core arithmetic

capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit by

16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle.

The 16-bit ALU is enhanced with integer divide assist hardware that supports an iterative

non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping

mechanism, and a selection of iterative divide instructions, to support 32-bit (or 16-bit) divided by

16-bit integer signed and unsigned division. All divide operations require 19 cycles to complete,

but are interruptible at any cycle boundary.

The PIC24F has a vectored exception scheme with up to 8 sources of non-maskable traps and

interrupt sources. Each interrupt source can be assigned to one of seven priority levels.

A block diagram of the CPU is shown in Figure 2-1.

Produkt Specifikationer

Mærke:	Microchip
Kategori:	Ikke kategoriseret
Model:	PIC24F32KA304

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