Microchip PIC24FJ32GA004 Manual
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PIC24FJ32GA004
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© 2008 Microchip Technology Inc. DS39768D-page 1
PIC24FJXXXGA0XX
1.0 DEVICE OVERVIEW
This document defines the programming specification
for the PIC24FJXXXGA0XX family of 16-bit micro-
controller devices. This programming specification is
required only for those developing programming support
for the PIC24FJXXXGA0XX family. Customers using
only one of these devices should use development
tools that already provide support for device
programming.
This specification includes programming specifications
for the following devices:
2.0 PROGRAMMING OVERVIEW
OF THE PIC24FJXXXGA0XX
FAMILY
There are two methods of programming the
PIC24FJXXXGA0XX family of devices discussed in
this programming specification. They are:
• In-Circuit Serial Programming™ (ICSP™)
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the chip.
The Enhanced In-Circuit Serial Programming
(Enhanced ICSP) protocol uses a faster method that
takes advantage of the programming executive, as
illustrated in Figure 2-1. The programming executive
provides all the necessary functionality to erase, pro-
gram and verify the chip through a small command set.
The command set allows the programmer to program
the PIC24FJXXXGA0XX devices without having to
deal with the low-level programming protocols of the
chip.
FIGURE 2-1: PROGRAMMING SYSTEM
OVERVIEW FOR
ENHANCED ICSP™
This specification is divided into major sections that
describe the programming methods independently.
Section 4.0 “Device Programming – Enhanced
ICSP” describes the Run-Time Self-Programming
(RTSP) method. Section 3.0 “Device Programming –
ICSP” describes the In-Circuit Serial Programming
method.
2.1 Power Requirements
All devices in the PIC24FJXXXGA0XX family are dual
voltage supply designs: one supply for the core and
peripherals and another for the I/O pins. A regulator is
provided on-chip to alleviate the need for two external
voltage supplies.
All of the PIC24FJXXXGA0XX devices power their core
digital logic at a nominal 2.5V. To simplify system
design, all devices in the PIC24FJXXXGA0XX family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
• PIC24FJ16GA002 • PIC24FJ96GA006
• PIC24FJ16GA004 • PIC24FJ96GA008
• PIC24FJ32GA002 • PIC24FJ96GA010
• PIC24FJ32GA004 • PIC24FJ128GA006
• PIC24FJ48GA002 • PIC24FJ128GA008
• PIC24FJ48GA004 • PIC24FJ128GA010
• PIC24FJ64GA002
• PIC24FJ64GA004
• PIC24FJ64GA006
• PIC24FJ64GA008
• PIC24FJ64GA010
PIC24FJXXXGA0XX
Programmer Programming
Executive
On-Chip Memory
PIC24FJXXXGA0XX Flash Programming Specification
PIC24FJXXXGA0XX
DS39768D-page 2 © 2008 Microchip Technology Inc.
The regulator provides power to the core from the other
VDD pins. A low-ESR capacitor (such as tantalum) must
be connected to the VDDCORE pin (Figure 2-2 and
Figure 2-3). This helps to maintain the stability of the
regulator. The specifications for core voltage and capac-
itance are listed in Section 7.0 “AC/DC Characteristics
and Timing Requirements”.
FIGURE 2-2: CONNECTIONS FOR THE
ON-CHIP REGULATOR
(64/80/100-PIN DEVICES)
FIGURE 2-3: CONNECTIONS FOR THE
ON-CHIP REGULATOR
(28/44-PIN DEVICES)
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
CEFC
3.3V
Regulator Enabled (ENVREG tied to VDD):
(10 μF typ)
Note 1: These are typical operating voltages. Refer
to
Section 7.0 “AC/DC Characteristics and
Timing Requirements”
for the full operating
ranges of VDD and VDDCORE.
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
3.3V(1)
2.5V(1)
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
2.5V(1)
Regulator Disabled (VDD tied to VDDCORE):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
3.3V(1)
2.5V (1)
Regulator Disabled (DISVREG tied to VDD):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
2.5V(1)
Regulator Disabled (VDD tied to VDDCORE):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
CEFC
3.3V
(10 μF typ)
Regulator Enabled (DISVREG tied to V SS):
Note 1: These are typical operating voltages. Refer
to
Section 7.0 “AC/DC Characteristics and
Timing Requirements”
for the full operating
ranges of VDD and VDDCORE.
© 2008 Microchip Technology Inc. DS39768D-page 3
PIC24FJXXXGA0XX
2.2 Program Memory Write/Erase
Requirements
The Flash program memory on the PIC24FJXXXGA0XX
devices has a specific write/erase requirement that must
be adhered to for proper device operation. The rule is
that any given word in memory must not be written more
than twice before erasing the page in which it is located.
Thus, the easiest way to conform to this rule is to write
all the data in a programming block within one write
cycle. The programming methods specified in this
specification comply with this requirement.
2.3 Pin Diagrams
The pin diagrams for the PIC24FJXXXGA0XX family
are shown in the following figures. The pins that are
required for programming are listed in Table 2-1 and
are shown in bold letters in the figures. Refer to the
appropriate device data sheet for complete pin
descriptions.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)
Note: Writing to a location multiple times without
erasing is not recommended.
Pin Name
During Programming
Pin Name Pin Type Pin Description
MCLR MCLR P Programming Enable
ENVREG ENVREG I Enable for On-Chip Voltage Regulator
DISVREG(1) DISVREG I Disable for On-Chip Voltage Regulator
VDD and AVDD(2) VDD P Power Supply
VSS and AVSS(2) VSS P Ground
VDDCORE VDDCORE P Regulated Power Supply for Core
PGC1 PGC I Primary Programming Pin Pair: Serial Clock
PGD1 PGD I/O Primary Programming Pin Pair: Serial Data
PGC2 PGC I Secondary Programming Pin Pair: Serial Clock
PGD2 PGD I/O Secondary Programming Pin Pair: Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: Applies to 28 and 44-pin devices only.
2: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).
PIC24FJXXXGA0XX
DS39768D-page 4 © 2008 Microchip Technology Inc.
Pin Diagrams
PIC24FJXXGA002
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin PDIP, SSOP, SOIC
28-Pin QFN(1)
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
PIC24FJXXGA002
5
4
MCLR
VSS
VDD
RA0
RA1
PGD1 RP0/EMUD1/AN2/C2IN-/ /CN4/RB0
RA4
RB4
RA3
RA2
RB3
RB2
PGC1 RP1/EMUC1/AN3/C2IN+/ /CN5/RB1
PGD3 RP5/EMUD3/ /SDA1/CN27/PMD7/RB5
VDD
VSS
PGC3 RP6/EMUC3/ /SCL1/CN24/PMD6/RB6
DISVREG
VCAP DDCORE/V
RB7
RB9
RB8
RB15
RB14
RB13
RB12
PGD2 RP10/EMUD2/TDI/ /CN16/PMD2/RB10
PGC2 RP11/EMUC2/TMS/ /CN15/PMD1/RB11
VSS
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
RA3
RA2
RB3
RB2
PGC1 RP1/EMUC1/AN3/C2IN+/ /CN5/RB1
DISVREG
VCAP DDCORE/V
RB9
RB13
RB12
PGD2 RP10/EMUD2/TDI/ /CN16/PMD2/RB10
PGC2 RP11/EMUC2/TMS/ /CN15/PMD1/RB11
VDD
PGC3 RP6/EMUC3/ /SCL1/CN24/PMD6/RB6
RA4
RB4
RB7
RB8
PGD3 RP5/EMUD3/ /SDA1/CN27/PMD7/RB5
MCLR
RA0
RA1
VDD
Vss
RB15
RB14
Legend: RPx represents remappable peripheral pins.
Note 1: The bottom pad of QFN packages should be connected to V SS.
© 2008 Microchip Technology Inc. DS39768D-page 5
PIC24FJXXXGA0XX
Pin Diagrams (Continued)
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC24FJXXGA004
37
44-Pin QFN(1)
RB8
RB7
PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6
PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5
VDD
RA9
RA4
VSS
RC5
RC4
RC3
RB12
PGC2/EMUC2/RP11/CN15/PMD1/RB11
PGD2 RP10/EMUD2/ /CN16/PMD2/RB10
VCAP DDCORE/V
DISVREG
RC9
RC8
RC7
RC6
RB9
RB13 RB2
RB3
RC0
RC1
RC2
RB4
VDD
VSS
RA2
RA3
RA8
PGC1 RP1/EMUC1/AN3/C2IN+/ /CN5/RB1
PGD1 RP0/EMUD1/AN2/C2IN-/ /CN4/RB0
RA1
RA0
MCLR
RA10
AVDD
AVSS
RB15
RB14
RA7
Legend: RPx represents remappable peripheral pins.
Note 1: The bottom pad of QFN packages should be connected to V SS.
© 2008 Microchip Technology Inc. DS39768D-page 7
PIC24FJXXXGA0XX
Pin Diagrams (Continued)
64-Pin TQFP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
22
44
24
25
26
27
28
29
30
31
32
PIC24FJXXGA006
1
46
45
23
43
42
41
40
39
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RF0
VCAP DDCORE/V
RC13
RD0
RD10
RD9
RD8
RD11
RC15
RC12
VDD
RG2
RF6
RF2
RF3
RG3
RC14
AVDD
RB8
RB9
RB10
RB11
VDD
PGC2/EMUC2/AN6/OCFA/RB6
PGD2/EMUD2/AN7/RB7
RF5
RF4
RE5
RE6
RE7
RG6
VDD
RB5
RB4
RB3
RB2
RG7
RG8
PGC1/EMUC1/VREF-/AN1/CN3/RB1
PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0
RG9
MCLR
RB12
RB13
RB14
RB15
RE0
RF1
RD7
VSS
VSS
Vss
ENVREG
63
62
61
59
60
58
57
56
54
55
53
52
51
49
50
38
37
34
36
35
33
17
19
20
21
18
AVSS
64
PIC24FJXXXGA006
PIC24FJXXXGA0XX
DS39768D-page 8 © 2008 Microchip Technology Inc.
Pin Diagrams (Continued)
80
79
78
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
60
59
26
56
40
39
28
29
30
31
32
33
34
35
36
37
38
PIC24FJXXGA008
17
18
19
1
76
77
58
57
27
55
54
53
52
51
RD5
RD4
RD13
RD12
RD3
RD2
RD1
RE2
RE1
RE0
RG0
RE4
RE3
RF0
VCAP DDCORE/V
RC13
RD0
RD10
RD9
RD8
RD11
RA15
RA14
RC15
RC12
VDD
RG2
RF6
RF7
RF8
RG3
RF2
RF3
RC14
PMA6/VREF+/RA10
PMA7/VREF-/RA9
AVDD
RB8
RB9
PMA13/CVREF/AN10/RB10
RB11
VDD
RD14
RD15
PGC2/EMUC2/AN6/OCFA/RB6
PGD2/EMUD2/AN7/RB7
RF5
RF4
RE5
RE6
RE7
RC1
RC3
RG6
VDD
RE8
RE9
RB5
RB4
RB3
RB2
RG7
RG8
PGC1/EMUC1/AN1/CN3/RB1
PGD1/EMUD1/AN0/CN2/RB0
RG9
MCLR
RB12
RB13
RB14
RB15
RG1
RF1
RD7
RD6
VSS
VSS
VSS
ENVREG
75
74
73
71
72
70
69
68
66
67
65
64
63
61
62
50
49
46
48
47
45
44
43
42
41
21
23
24
25
22
AVSS
80-Pin TQFP
PIC24FJXXXGA008
© 2008 Microchip Technology Inc. DS39768D-page 9
PIC24FJXXXGA0XX
Pin Diagrams (Continued)
92
94
93
91
90
89
88
87
86
85
84
83
82
81
80
79
78
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
56
45
44
43
42
41
40
39
28
29
30
31
32
33
34
35
36
37
38
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67
66
75
74
73
58
57
24
23
25
96
98
97
99
27
46
47
48
49
55
54
53
52
51
100
RD5
RD4
RD13
RD12
RD3
RD2
RD1
RA7
RA6
RE2
RG13
RG12
RG14
RE1
RE0
RG0
RE4
RE3
RF0
RC13
RD0
RD10
RD9
RD8
RD11
RF2
RA14
RC15
RC12
VDD
RG2
RF6
RF7
RF8
RG3
RF2
RF3
VSS
RC14
RA10
PMA7/VREF-/RA9
AVDD
AVSS
RB8
RB9
RB10
RB11
VDD
RF12
RF13
RD14
RD15
VDD
VSS
PGC2/EMUC2/AN6/OCFA/RB6
PGD2/EMUD2/AN7/RB7
RF5
RF4
RE5
RE6
RE7
RC1
RC2
RC3
RC4
RG6
VDD
RA0
RE8
RE9
RB5
RB4
RB3
RB2
RG7
RG8
PGC1/EMUC1/AN1/CN3/RB1
PGD1/EMUD1/AN0/CN2/RB0
VDD
RG15
PRG9
MCLR
RB12
RB13
RB14
RB15
RG1
RF1
ENVREG
RD6
TDO
RA3
RA2
VSS
VSS
VSS
VCAP/VDDCORE
TDI
RA1
100-Pin TQFP
50
26
RD7
PIC24FJXXGA010
PIC24FJXXXGA010
PIC24FJXXXGA0XX
DS39768D-page 10 © 2008 Microchip Technology Inc.
2.4 Memory Map
The program memory map extends from 000000h to
FFFFFEh. Code storage is located at the base of the
memory map and supports up to 44K instruction words
(about 128 Kbytes). Table 2-3 shows the program
memory size and number of erase and program blocks
present in each device variant. Each erase block, or
page, contains 512 instructions, and each program
block, or row, contains 64 instructions.
Locations 800000h through 8007FEh are reserved for
executive code memory. This region stores the
programming executive and the debugging executive.
The programming executive is used for device pro-
gramming and the debugging executive is used for
in-circuit debugging. This region of memory can not be
used to store user code.
The last two implemented program memory locations
are reserved for the device Configuration registers.
TABLE 2-2: FLASH CONFIGURATION
WORD LOCATIONS FOR
PIC24FJXXXGA0XX DEVICES
Locations, FF0000h and FF0002h, are reserved for the
Device ID registers. These bits can be used by the
programmer to identify what device type is being
programmed. They are described in Section 6.1
“Device ID”. The Device ID registers read out
normally, even after code protection is applied.
Figure 2-4 shows the memory map for the
PIC24FJXXXGA0XX family variants.
TABLE 2-3: CODE MEMORY SIZE
Device
Configuration Word
Addresses
1 2
PIC24FJ16GA 002BFEh 002BFCh
PIC24FJ32GA 0057FEh 0057FCh
PIC24FJ48GA 0083FEh 0083FCh
PIC24FJ64GA 00ABFEh 00ABFCh
PIC24FJ96GA 00FFFEh 00FFFCh
PIC24FJ128GAGA 0157FEh 0157FCh
Device
User Memory
Address Limit
(Instruction Words)
Write
Blocks
Erase
Blocks
PIC24FJ16GA 002BFEh (5.5K) 88 11
PIC24FJ32GA 0057FEh (11K) 176 22
PIC24FJ48GA 0083FEh (16.5K) 264 33
PIC24FJ64GA 00ABFEh (22K) 344 43
PIC24FJ96GA 00FFFEh (32K) 512 64
PIC24FJ128GA 0157FEh (44K) 688 86
Produkt Specifikationer
| Mærke: | Microchip |
| Kategori: | Ikke kategoriseret |
| Model: | PIC24FJ32GA004 |
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