Microchip PIC24HJ128GP506A Manual

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Analog-to-Digital

Converter (ADC)

Section 16. Analog-to-Digital Converter (ADC)

HIGHLIGHTS

This section of the manual contains the following major topics:

16.1 Introduction .................................................................................................................. 16-2

16.2 Control Registers ......................................................................................................... 16-6

16.3 Overview of Sample and Conversion Sequence ....................................................... 16-17

16.4 ADC Configuration..................................................................................................... 16-27

16.5 ADC Interrupt Generation .......................................................................................... 16-33

16.6 Analog Input Selection for Conversion....................................................................... 16-35

16.7 Specifying Conversion Results Buffering for Devices with DMA................................ 16-44

16.8 ADC Configuration Example ...................................................................................... 16-48

16.9 ADC Configuration for 1.1 Msps ................................................................................16-49

16.10 Sample and Conversion Sequence Examples for Devices without DMA .................. 16-51

16.11 Sample and Conversion Sequence Examples for Devices with DMA ....................... 16-63

16.12 Analog-to-Digital Sampling Requirements ................................................................. 16-73

16.13 Reading the ADC Result Buffer .................................................................................16-74

16.14 Transfer Functions ..................................................................................................... 16-76

16.15 ADC Accuracy/Error................................................................................................... 16-78

16.16 Connection Considerations........................................................................................ 16-78

16.17 Operation During Sleep and Idle Modes .................................................................... 16-79

16.18 Effects of a Reset....................................................................................................... 16-79

16.19 Special Function Registers ........................................................................................ 16-80

16.20 Design Tips ................................................................................................................ 16-81

16.21 Related Application Notes.......................................................................................... 16-82

16.22 Revision History ......................................................................................................... 16-83

dsPIC33F/PIC24H Family Reference Manual

16.1 INTRODUCTION

This document describes the features and associated operational modes of the Successive

Approximation (SAR) Analog-to-Digital Converter (ADC) available on the dsPIC33F/PIC24H

families of devices.

The ADC module can be configured by the user application to function as a 10-bit, 4-channel

ADC (for devices with 10-bit only ADC) or a 12-bit, single-channel ADC (for devices with

selectable 10-bit or 12-bit ADC).

Figure 16-1 illustrates a block diagram of the ADC module for devices with DMA. Figure 16-2

illustrates a block diagram of the ADC module for devices without DMA.

The dsPIC33F/PIC24H ADC module has the following key features:

• SAR conversion

• Up to 1.1 Msps conversion speed

• Up to 32 analog input pins

• External voltage reference input pins

• Four unipolar differential Sample and Hold (S&H) amplifiers

• Simultaneous sampling of up to four analog input pins

• Automatic Channel Scan mode

• Selectable conversion trigger source

• Up to 16-word conversion result buffer

• Selectable Buffer Fill modes (not available on all devices)

• DMA support, including Peripheral Indirect Addressing (not available on all devices)

• Operation during CPU Sleep and Idle modes

Depending on the device variant, the ADC module may have up to 32 analog input pins,

designated AN0-AN31. These analog inputs are connected by multiplexers to four S&H

amplifiers, designated CH0-CH3. The analog input multiplexers have two sets of control bits,

designated as MUXA (CHySA/CHyNA) and MUXB (CHySB/CHyNB). These control bits select a

particular analog input for conversion. The MUXA and MUXB control bits can alternatively select

the analog input for conversion. Unipolar differential conversions are possible on all channels

using certain input pins (see Figure 16-1 Figure 16-2 and ).

Channel Scan mode can be enabled for the CH0 S&H amplifier. Any subset of the analog inputs

(AN0 to AN31 based on availability) can be selected by the user application. The selected inputs

are converted in ascending order using CH0.

The ADC module supports simultaneous sampling using multiple S&H channels to sample the

inputs at the same time, and then performs the conversion for each channel sequentially. By

default, the multiple channels are sampled and converted sequentially.

For devices with DMA, the ADC module is connected to a single-word result buffer. However,

multiple conversion results can be stored in a DMA RAM buffer with no CPU overhead when

DMA is used with the ADC module. Each conversion result is converted to one of four 16-bit

output formats when it is read from the buffer.

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all dsPIC33F/PIC24H devices.

Please consult the note at the beginning of the “Analog-to-Digital Converter

(ADC)” chapter in the current device data sheet to check whether this document

supports the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

For devices without DMA, the ADC module is connected to a 16-word result buffer. The ADC

result is available in four different numerical formats (see Figure 16-14).

Note 1: A ‘y’ is used with MUXA and MUXB control bits to specify the S&H channel numbers

(y = 0 or 123).

2: Depending on a particular device pinout, the ADC can have up to 32 analog input

pins, designated AN0 through AN31. In addition, there are two analog input pins for

external voltage reference connections (VREF+, VREF-). These voltage reference

inputs can be shared with other analog input pins. The actual number of analog

input pins and external voltage reference input configuration depends on the

specific device. For further details, refer to the specific device data sheet.

dsPIC33F/PIC24H Family Reference Manual

Figure 16-1: ADC Block Diagram for Devices with DMA

SAR ADC

S/H0

S/H1

AN0

AN31

AN1

VREFL

CH0SB<4:0>

CH0NA CH0NB

AN0

AN3

CH123SA

AN9

VREFL

CH123SB

CH123NA CH123NB

AN6

S/H2

AN1

AN4

CH123SA

AN10

VREFL

CH123SB

CH123NA CH123NB

AN7

S/H3

AN2

AN5

CH123SA

AN11

VREFL

CH123SB

CH123NA CH123NB

AN8

CH1(2)

CH0

CH2(2)

CH3(2)

CH0SA<4:0>

CHANNEL

SCAN

CSCNA

Alternate

Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. For details, refer to the “Pin Diagrams” section in the specific device

data sheet.

2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

Input Selection

VREFH VREFL

V +REF (1) AV AVDD SS

V -REF (1)

VCFG<2:0>

Bus Interface

ADC1BUF0

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

Figure 16-2: ADC Block Diagram for Devices without DMA

SAR ADC

S/H0

S/H1

ADC1BUF0

ADC1BUF1

ADC1BUF2

ADC1BUFF

ADC1BUFE

AN0

AN31

AN1

VREFL

CH0SB<4:0>

CH0NA CH0NB

AN0

AN3

CH123SA

AN9

VREFL

CH123SB

CH123NA CH123NB

AN6

S/H2

AN1

AN4

CH123SA

AN10

VREFL

CH123SB

CH123NA CH123NB

AN7

S/H3

AN2

AN5

CH123SA

AN11

VREFL

CH123SB

CH123NA CH123NB

AN8

CH1(2)

CH0

CH2(2)

CH3(2)

CH0SA<4:0>

CHANNEL

SCAN

CSCNA

Alternate

Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. For details, refer to the “Pin Diagrams” section in the specific device

data sheet.

2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

Input Selection

VREFH VREFL

V +REF (1) AV AVDD SS

V -REF (1)

VCFG<2:0>

dsPIC33F/PIC24H Family Reference Manual

16.2 CONTROL REGISTERS

The ADC module has ten Control and Status registers. These registers are:

•ADxCON1: ADCx Control Register 1

•ADxCON2: ADCx Control Register 2

•ADxCON3: ADCx Control Register 3

•ADxCON4: ADCx Control Register 4

•ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register

•ADxCHS0: ADCx Input Channel 0 Select Register

•AD1CSSH: ADC1 Input Scan Select Register High

•ADxCSSL: ADCx Input Scan Select Register Low

•AD1PCFGH: ADC1 Port Configuration Register High

•ADxPCFGL: ADCx Port Configuration Register Low

The ADxCON1, ADxCON2 and ADxCON3 registers control the operation of the ADC module.

The ADxCON4 register sets up the number of conversion results stored in a DMA buffer for each

analog input in the Scatter/Gather mode for devices with DMA. The ADxCHS123 and ADxCHS0

registers select the input pins to be connected to the S&H amplifiers. The ADCSSH/L registers

select inputs to be sequentially scanned. The ADxPCFGH/L registers configure the analog input

pins as analog inputs or as digital I/O.

16.2.1 ADC Result Buffer

For devices with DMA, the ADC module contains a single-word result buffer, ADC1BUF0. For

devices without DMA, the ADC module contains a 16-word dual-port RAM, to buffer the results.

The 16 buffer locations are referred to as ADC1BUF0, ADC1BUF1, ADC1BUF2, ..., ADC1BUFE

and ADC1BUFF.

Note: After a device reset, the ADC buffer register(s) will contain unknown data.

Section 16. Analog-to-Digital Converter (ADC)

Analog-to-Digital

Converter (ADC)

R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

ADON — ADSIDL ADDMABM(2) — AD12B(2) FORM<1:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

HC,HS

R/C-0

HC, HS

SSRC<2:0> — SIMSAM ASAM SAMP DONE

bit 7 bit 0

Legend: HC = Cleared by hardware HS = Set by hardware C = Clear only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADON: ADC Operating Mode bit

1 = ADC module is operating

0 = ADC is off

bit 14 Unimplemented: Read as ‘0’

bit 13 ADSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 ADDMABM: DMA Buffer Build Mode bit(3)

1 = DMA buffers are written in the order of conversion. The module provides an address to the DMA

channel that is the same as the address used for the non-DMA stand-alone buffer

0 = DMA buffers are written in Scatter/Gather mode. The module provides a Scatter/Gather address to

the DMA channel, based on the index of the analog input and the size of the DMA buffer

bit 11 Unimplemented: Read as ‘0’

bit 10 AD12B: 10-bit or 12-bit Operation Mode bit(2)

1 = 12-bit, 1-channel ADC operation

0 = 10-bit, 4-channel ADC operation

bit 9-8 FORM<1:0>: Data Output Format bits

For 10-bit operation:

11 sddd dddd dd00 0000 = Signed fractional (DOUT = , where s d = sign, = data)

10 = Fractional (DOUT = dddd dddd dd00 0000)

01 ssss sssd dddd dddd = Signed integer (DOUT = , where s d = sign, = data)

00 = Integer (DOUT = 0000 00dd dddd dddd)

For 12-bit operation:

11 sddd dddd dddd 0000 = Signed fractional (DOUT = , where s d = sign, = data)

10 = Fractional (DOUT = dddd dddd dddd 0000)

01 ssss sddd dddd dddd = Signed Integer (DOUT = , where s = sign, d = data)

00 = Integer (DOUT = 0000 dddd dddd dddd)

bit 7-5 SSRC<2:0>: Sample Clock Source Select bits

111 = Internal counter ends sampling and starts conversion (auto-convert)

110 = Reserved

101 = Motor Control PWM2 interval ends sampling and starts conversion(1)

100 = GP timer (Timer5 for ADC1, Timer3 for ADC2) compare ends sampling and starts conversion

(2)

011 = Motor Control PWM1 interval ends sampling and starts conversion(1)

010 = GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion

001 = Active transition on INT0 pin ends sampling and starts conversion

000 = Clearing sample bit ends sampling and starts conversion

bit 4 Unimplemented: Read as ‘0’

Note 1: This clock source is not available on all devices. Refer to the specific device data sheet for availability.

2: This bit is not available on all devices. Refer to the “Analog-to-Digital Converter” chapter in the specific

device data sheet for availability.

dsPIC33F/PIC24H Family Reference Manual

bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 1x or )

When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’

1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or

Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)

0 = Samples multiple channels individually in sequence

bit 2 ASAM: ADC Sample Auto-Start bit

1 = Sampling begins immediately after last conversion. SAMP bit is auto-set

0 = Sampling begins when SAMP bit is set

bit 1 SAMP: ADC Sample Enable bit

1 = ADC S&H amplifiers are sampling

0 = ADC S&H amplifiers are holding

If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.

If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,

automatically cleared by hardware to end sampling and start conversion.

bit 0 DONE: ADC Conversion Status bit

1 = ADC conversion cycle is completed

0 = ADC conversion not started or in progress

Automatically set by hardware when analog-to-digital conversion is complete. Software can write ‘0’ to

clear DONE status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation

in progress. Automatically cleared by hardware at the start of a new conversion.

Note 1: This clock source is not available on all devices. Refer to the specific device data sheet for availability.

2: This bit is not available on all devices. Refer to the “Analog-to-Digital Converter” chapter in the specific

device data sheet for availability.

Produkt Specifikationer

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Model:	PIC24HJ128GP506A

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