Microchip PIC32MX695F512L Manual

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Section 35. Ethernet Controller

This section of the manual contains the following major topics:

35.1 Introduction .............................................................................................................. 35-2

35.2 Ethernet Controller Overview .................................................................................. 35-3

35.3 Status and Control Registers................................................................................... 35-4

35.4 Operation...............................................................................................................35-43

35.5 Ethernet Interrupts................................................................................................. 35-82

35.6 Operation in Power-Saving and Debug Modes ..................................................... 35-87

35.7 Effects of Various Resets....................................................................................... 35-90

35.8 I/O Pin Control ....................................................................................................... 35-91

35.9 Related Application Notes ..................................................................................... 35-92

35.10 Revision History..................................................................................................... 35-93

PIC32 Family Reference Manual

35.1 INTRODUCTION

The Ethernet Controller is a bus master module that interfaces with an off-chip PHY to implement

a complete Ethernet node in an embedded system.

The following are key features of the Ethernet Controller module:

• Supports 10/100 Mbps data transfer rates (see the Caution note in 35.4 “Operation”)

• Supports the full-duplex and half-duplex operation

• Supports the Reduced Media Independent Interface (RMII) and Media Independent

Interface (MII) PHY interface

• Supports the MII Management (MIIM) PHY Management interface

• Supports manual and automatic Flow Control

• Supports Auto-MDIX and enabled PHYs

• RAM descriptor based Direct Memory Access (DMA) operation for receive and transmit

path

• Fully configurable interrupts

• Configurable receive packet filtering

- Cyclic Redundancy Check (CRC)

- 64-byte pattern match

- Broadcast, multicast, and unicast packets

- Magic Packet™

- 64-bit Hash table

- Runt packet

• Supports Packet Payload Checksum calculation

• Supports various hardware statistics counters

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “Ethernet Controller” chapter in

the current device data sheet to check whether this document supports the device

you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Note: To avoid cache coherency problems on devices with L1 cache, it is recommended

to access the Ethernet buffers from the KSEG1 segment.

PIC32 Family Reference Manual

35.3 STATUS AND CONTROL REGISTERS

The Ethernet Controller module consists of the following Special Function Registers (SFRs):

Controller and DMA Engine Configuration/Status Registers:

•ETHCON1: Ethernet Controller Control 1 Register

•ETHCON2: Ethernet Controller Control 2 Register

•ETHTXST: Ethernet Controller TX Packet Descriptor Start Address Register

•ETHRXST: Ethernet Controller RX Packet Descriptor Start Address Register

•ETHIEN: Ethernet Controller Interrupt Enable Register

•ETHIRQ: Ethernet Controller Interrupt Request Register

•ETHSTAT: Ethernet Controller Status Register

RX Filtering Configuration Registers:

•ETHRXFC: Ethernet Controller Receive Filter Configuration Register

•ETHHT0: Ethernet Controller Hash Table 0 Register

•ETHHT1: Ethernet Controller Hash Table 1 Register

•ETHPMM0: Ethernet Controller Pattern Match Mask 0 Register

•ETHPMM1: Ethernet Controller Pattern Match Mask 1 Register

•ETHPMCS: Ethernet Controller Pattern Match Checksum Register

•ETHPMO: Ethernet Controller Pattern Match Offset Register

Flow Control Configuring Register:

•ETHRXWM: Ethernet Controller Receive Watermarks Register

Ethernet Statistics Registers:

•ETHRXOVFLOW: Ethernet Controller Receive Overflow Statistics Register

•ETHFRMTXOK: Ethernet Controller Frames Transmitted Okay Statistics Register

•ETHSCOLFRM: Ethernet Controller Single Collision Frames Statistics Register

•ETHMCOLFRM: Ethernet Controller Multiple Collision Frames Statistics Register

•ETHFRMRXOK: Ethernet Controller Frames Received Okay Statistics Register

•ETHFCSERR: Ethernet Controller Frame Check Sequence Error Statistics Register

•ETHALGNERR: Ethernet Controller Alignment Errors Statistics Register

MAC Configuration Registers:

•EMAC1CFG1: Ethernet Controller MAC Configuration 1 Register

•EMAC1CFG2: Ethernet Controller MAC Configuration 2 Register

•EMAC1IPGT: Ethernet Controller MAC Back-to-Back Interpacket Gap Register

•EMAC1IPGR: Ethernet Controller MAC Non-Back-to-Back Interpacket Gap Register

•EMAC1CLRT: Ethernet Controller MAC Collision Window/Retry Limit Register

•EMAC1MAXF: Ethernet Controller MAC Maximum Frame Length Register

•EMAC1SUPP: Ethernet Controller MAC PHY Support Register

•EMAC1TEST: Ethernet Controller MAC Test Register

•EMAC1SA0: Ethernet Controller MAC Address 0 Register

•EMAC1SA1: Ethernet Controller MAC Address 1 Register

•EMAC1SA2: Ethernet Controller MAC Address 2 Register

MII Management Registers:

•EMAC1MCFG: Ethernet Controller MAC MII Management Configuration Register

•EMAC1MCMD: Ethernet Controller MAC MII Management Command Register

•EMAC1MADR: Ethernet Controller MAC MII Management Address Register

•EMAC1MWTD: Ethernet Controller MAC MII Management Write Data Register

•EMAC1MRDD: Ethernet Controller MAC MII Management Read Data Register

•EMAC1MIND: Ethernet Controller MAC MII Management Indicators Register

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTV<15:8>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTV<7:0>

15:8

R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

ON — SIDL — — — TXRTS RXEN

(1)

7:0

R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0

AUTOFC — — MANFC — — — BUFCDEC

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 PTV<15:0>: PAUSE Timer Value bits

This register should be written only when the RXEN bit (ETHCON1<8>) is not set. These bits are only used

for Flow Control operations.

bit 15 ON: Ethernet ON bit

1 = Ethernet module is enabled

0 = Ethernet module is disabled

bit 14 Read as ‘Unimplemented: 0’

bit 13 SIDL: Ethernet Stop in Idle Mode bit

1 = Ethernet module transfers are suspended during Idle mode

0 = Ethernet module transfers continue during Idle mode

bit 12-10 Read as ‘Unimplemented: 0’

bit 9 TXRTS: Transmit Request to Send bit

1 = Activate the transmit logic and send the packets defined in the TX Ethernet Descriptor Table (EDT)

0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)

After the bit is written with a ‘1 0’, it will clear to ‘ ’ whenever the transmit logic has finished transmitting the

requested packets in the EDT. If ‘0’ is written by the CPU, the transmit logic finishes the current packet’s

transmission, and then stops any further transmission.

This bit only affects TX operations.

bit 8 RXEN: Receive Enable bit

(1)

1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter configuration

0 = Disable RX logic, no packets are received in the RX buffer

This bit only affects RX operations.

bit 7 AUTOFC: Automatic Flow Control bit

1 = Automatic Flow Control is enabled

0 = Automatic Flow Control is disabled

Setting this bit will enable the automatic Flow Control. If set, the full and empty watermarks are used to

automatically enable and disable the Flow Control. When the number of received buffers BUFCNT<7:0> bits

(ETHSTAT<23:16>) rises to the full watermark, Flow Control is automatically enabled. When the BUFCNT

falls to the empty watermark, Flow Control is automatically disabled.

This bit is only used for Flow Control operations, and affects both TX and RX operations.

bit 6-5 Unimplemented: Read as ‘0’

Note 1: It is not recommended to clear the RXEN bit, and then make changes to any RX related field/register. The

Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.

Section 35. Ethernet Controller

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RXFWM<7:0>

15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RXEWM<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-16 RXFWM<7:0>: Receive Full Watermark bits

The software controlled RX Buffer Full Watermark Pointer is compared against the RX BUFCNT to deter-

mine the full watermark condition for the FWMARK interrupt and for enabling Flow Control when automatic

Flow Control is enabled. The Full Watermark Pointer should be greater than the Empty Watermark Pointer.

bit 15-8 Unimplemented: Read as ‘0’

bit 7-0 RXEWM<7:0>: Receive Empty Watermark bits

The software controlled RX Buffer Empty Watermark Pointer is compared against the RX BUFCNT to

determine the empty watermark condition for the EWMARK interrupt and for disabling Flow Control when

automatic Flow Control is enabled. The Empty Watermark Pointer should be less than the Full Watermark

Pointer.

Note: This register is only used for RX operations .

Section 35. Ethernet Controller

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

— TXBUSE

(1)

RXBUSE

(2)

— — — EWMARK

(2)

FWMARK

(2)

7:0

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

RXDONE

(2)

PKTPEND

(2)

RXACT

(2)

— TXDONE

(1)

TXABORT

(1)

RXBUFNA

(2)

RXOVFLW

(2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as ‘0’

bit 14 TXBUSE: Transmit BVCI Bus Error Interrupt bit

(1)

1 = BVCI bus error occurred

0 = No BVCI error occurred

This bit is set when the TX DMA encounters a BVCI bus error during a system memory access. It is cleared

by either a Reset or CPU write of a ‘1’ to the CLR register.

bit 13 RXBUSE: Receive BVCI Bus Error Interrupt bit

(2)

1 = BVCI bus error occurred

0 = No BVC error occurred

This bit is set when the RX DMA encounters a BVCI bus error during a system memory access. It is cleared

by either a Reset or CPU write of a ‘1’ to the CLR register.

bit 12-10 Unimplemented: Read as ‘0’

bit 9 EWMARK: Empty Watermark Interrupt bit

(2)

1 = Empty Watermark pointer reached

0 = No interrupt pending

This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the RXEWM

<7:0>bits (ETHRXWM<7:0>). It is cleared by the BUFCNT<7:0> bits (ETHSTAT<23:16>) being

incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.

bit 8 FWMARK: Full Watermark Interrupt bit

(2)

1 = Full Watermark pointer reached

0 = No interrupt pending

This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the

RXFWM<7:0> bits (ETHRXWM<23:16>). It is cleared by writing the BUFCDEC bit (ETHCON1<0>) to dec-

rement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.

bit 7 RXDONE: Receive Done Interrupt bit

(2)

1 = RX packet was successfully received

0 = No interrupt pending

This bit is set whenever a RX packet is successfully received. It is cleared by either a Reset or CPU write of

a ‘1’ to the CLR register.

Note 1: This bit is only used for TX operations.

2: This bit is only used for RX operations.

Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or

clearing any bits in this register should be done only for debug/test purposes.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SCOLFRMCNT<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SCOLFRMCNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Read as ‘Unimplemented: 0’

bit 15-0 SCOLFRMCNT<15:0>: Single Collision Frame Count bits

Increment count for frames that were successfully transmitted on the second try.

Note 1: This register is only used for TX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for

bytes 0/1 are ‘0’.

3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or

clearing any bits in this register should only be done for debug/test purposes.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

MCOLFRMCNT<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

MCOLFRMCNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 MCOLFRMCNT<15:0>: Multiple Collision Frame Count bits

Increment count for frames that were successfully transmitted after there was more than one collision.

Note 1: This register is only used for TX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for

bytes 0/1 are ‘0’.

3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or

clearing any bits in this register should only be done for debug/test purposes.

Section 35. Ethernet Controller

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-1 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

SOFTRESET SIMRESET — — RESETRMCS RESETRFUN RESETTMCS RESETTFUN

7:0

U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1

— — — LOOPBACK TXPAUSE RXPAUSE PASSALL RXENABLE

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 SOFTRESET: Soft Reset bit

Setting this bit will put the MACMII in Reset. Its default value is ‘1’.

bit 14 SIMRESET: Simulation Reset bit

Setting this bit will cause a Reset to the random number generator within the Transmit Function.

bit 13-12 Unimplemented: Read as ‘0’

bit 11 RESETRMCS: Reset MCS/RX bit

Setting this bit will put the MAC Control Sub-layer/Receive domain logic in Reset.

bit 10 RESETRFUN: Reset RX Function bit

Setting this bit will put the MAC Receive function logic in Reset.

bit 9 RESETTMCS: Reset MCS/TX bit

Setting this bit will put the MAC Control Sub-layer/TX domain logic in Reset.

bit 8 RESETTFUN: Reset TX Function bit

Setting this bit will put the MAC Transmit function logic in Reset.

bit 7-5 Unimplemented: Read as ‘0’

bit 4 LOOPBACK: MAC Loopback mode bit

1 = MAC Transmit interface is loop backed to the MAC Receive interface

0 = MAC normal operation

bit 3 TXPAUSE: MAC TX Flow Control bit

1 = PAUSE Flow Control frames are allowed to be transmitted

0 = PAUSE Flow Control frames are blocked

bit 2 RXPAUSE: MAC RX Flow Control bit

1 = The MAC acts upon received PAUSE Flow Control frames

0 = Received PAUSE Flow Control frames are ignored

bit 1 PASSALL: MAC Pass all Receive Frames bit

1 = The MAC will accept all frames regardless of type (Normal vs. Control)

0 = The received Control frames are ignored

bit 0 RXENABLE: MAC Receive Enable bit

1 = Enable the MAC receiving of frames

0 = Disable the MAC receiving of frames

Note: 16-bit and 32-bit accesses to this register (including the Set, Clear and Invert registers) are allowed. 8-bit

accesses are not allowed and are ignored by hardware.

Section 35. Ethernet Controller

Table 35-2: Pad Operation

bit 5 PADENABLE: Pad/CRC Enable bit

(1,3)

1 = The MAC will pad all short frames

0 = The frames presented to the MAC have a valid length

bit 4 CRCENABLE: CRC Enable1 bit

1 = The MAC will append a CRC to every frame whether padding was required or not. Must be set if the

PADENABLE bit is set

0 = The frames presented to the MAC have a valid CRC

bit 3 DELAYCRC: Delayed CRC bit

This bit determines the number of bytes, if any, of proprietary header information that exist on the front of the

IEEE 802.3 frames.

1 = Four bytes of header (ignored by the CRC function)

0 = No proprietary header

bit 2 HUGEFRM: Huge Frame enable bit

1 = Frames of any length are transmitted and received

0 = Huge frames are not allowed for receive or transmit

bit 1 LENGTHCK: Frame Length checking bit

1 = Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field

represents a length then the check is performed. Mismatches are reported on the Transmit/Receive

Statistics Vector

0 = Length/Type field check is not performed

bit 0 FULLDPLX: Full-Duplex Operation bit

1 = The MAC operates in Full-Duplex mode

0 = The MAC operates in Half-Duplex mode

Type AUTOPAD VLANPAD PADENABLE Action

Any x x 0 No pad, check CRC

Any 0 0 1 Pad to 60 Bytes, append CRC

Any x 1 1 Pad to 64 Bytes, append CRC

Any 1 0 1 If untagged: Pad to 60 Bytes, append CRC

If VLAN tagged: Pad to 64 Bytes, append CRC

(Continued)

Note 1: This bit is ignored, if the PADENABLE bit is cleared.

2: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.

3: Table 35-2 provides a description of the pad function based on the configuration of this register.

Note: 16-bit and 32-bit accesses to this register (including the Set, Clear and Invert registers) are allowed. 8-bit

accesses are not allowed and are ignored by hardware.

PIC32 Family Reference Manual

35.4.1.7 FRAME CHECK SEQUENCE

The Frame Check Sequence (FCS) is a 4-byte field containing a standard 32-bit CRC calculated

over the Destination, Source, Type/Length, Data, and Padding fields. It allows for the detection

of transmission errors.

For transmitted frames, PIC32 devices can automatically generate and append a valid Flow

Control by using the CRC Enable1 bit, CRCENABLE (EMAC1CFG2<4>). Otherwise, the

software must calculate the CRC for the frame to be transmitted and append it properly.

For received frames, the FCS field is stored to the receive buffer. Frames with invalid CRC values

can either be discarded or accepted using the CRC Error and CRC Check Acceptance filters

described in 35.4.8.1 “CRC Error Acceptance Filter” and 35.4.8.3 “CRC Check Acceptance

Filter”.

Note: The polynomial for generating the FCS is:

G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 +x4 + p46-x2 + x + 1.

The FCS is transmitted starting with bit 31 and ending with bit 0.

Section 35. Ethernet Controller

35.4.2 Basic Ethernet Controller Operation

The Ethernet Controller is enabled by setting the Ethernet ON bit in the Ethernet Controller

Control 1 Register (ETHCON1<15>), and is disabled by resetting the same bit. This is the default

state after any Reset. If the Ethernet Controller is disabled, all of the I/O pins used for the

MII/RMII and MIIM interfaces operate as port pins, and are under the control of the respective

PORT latch bit and TRIS bit.

Disabling the controller resets the internal DMA state machines, and all transmit and receive

operations are aborted. The SFRs are still accessible and their values preserved.

Clearing the ON bit while the Ethernet Controller is active will abort all pending operations and

reset the peripheral, as defined above.

Re-enabling the ON bit will restart the Ethernet Controller in its clean reset state while preserving

the SFRs values.

35.4.3 MAC Overview

The MAC sub-layer is part of the functionality described in the Open Systems

Interconnection (OSI) model for the Data Link Layer. It defines a medium independent facility,

built on the medium dependent physical facility provided by the Physical Layer, and under the

access-layer-independent LLC sub-layer or other MAC client. It is applicable to a general class

of local area broadcast media suitable for use with the Carrier Sense Multiple Access with

Collision Detection (CSMA/CD).

The CSMA/CD MAC sub-layer provides services to the MAC client required for the transmission

and reception of frames. The CSMA/CD MAC sub-layer makes best effort to acquire the medium,

and transfer a serial stream of bits to the Physical Layer. Although, certain errors are reported to

the client, error recovery is not provided by the MAC.

The following is a summary of the functional capabilities of the CSMA/CD MAC sub-layer, see

Figure 35-3:

• For Frame transmission:

- Accepts data from the MAC client and constructs a frame

- Presents a bit-serial data stream to the Physical Layer for transmission on the medium

- In Half-Duplex mode, defers transmission of a bit-serial stream whenever the physical

medium is busy

- It can append proper FCS value to outgoing frames and verifies full byte boundary

alignment

- Delays transmission of frame bit-stream for specified Interframe Gap (IFG) period

- In Half-Duplex mode, halts transmission when collision is detected

- In Half-Duplex mode, schedules retransmission after a collision until a specified retry

limit is reached

- In Half-Duplex mode, enforces collision to ensure propagation throughout network by

sending jam message

- Adds preamble and Start-of-Frame Delimiter and appends FCS to all frame

- Appends PAD field for frames whose data length is less than the minimum value

Note 1: If the ON bit is cleared during an active internal bus transaction, the controller will

complete the current bus transaction before entering the disabled state. Once the

controller is disabled, the Transmit Busy bit (TXBUSY) in the Ethernet Controller

Status Register (ETHSTAT<6>) and the Receive Busy bit, RXBUSY

(ETHSTAT<5>), will reflect an inactive status.

2: Whenever the Ethernet Controller is reset through the ON bit, the software should

also reset the external PHY using the MIIM interface. This ensures the PHY is in a

known initialized state. In addition, the MAC should also be soft reset through the

Ethernet Controller MAC Configuration 1 Register (EMAC1CFG1).

Section 35. Ethernet Controller

35.4.6 Media Independent Interface Management (MIIM)

The Media Independent Interface Management (MIIM) module provides a serial communication

link between the PIC32 host and an external MII PHY device. The external serial

communications link operates in accordance with Clause 22 of the IEEE 802.3 Specification.

The MIIM input/output signals are:

• Management Data Clock (MDC) – MDC is sourced by the MAC to the PHY as the timing

reference for transfer of information on the MDIO signal.

• Management Data Input/Output (MDIO) – MDIO is a bidirectional signal between the PHY

and the MAC. It is used to transfer control information and status between the PHY and the

MAC. Control information is driven by the MAC synchronously with respect to MDC and is

sampled synchronously by the PHY. Status information is driven by the PHY synchronously

with respect to MDC and is sampled synchronously by the MAC.

The communication over the MIIM interface takes place in frames. Frames transmitted on the

MIIM have the following structure (see Table 35-6):

• Preamble: At the beginning of each transaction, the MAC sends a sequence of 32 logic one

bits on MDIO to provide the PHY with a synchronization pattern.

• SOF: The SOF is indicated by a <01> pattern

• Operation Code: <10> for a read transaction, <01> for a write transaction

• PHY Address: Five bits, allowing 32 unique PHY addresses. A PHY will always respond to

transactions with address zero.

• Register Address: Five bits, allowing 32 individual registers to be addressed within each PHY

• Turnaround: A 2-bit-time spacing between the Register Address field and the Data field of a

management frame to avoid contention during a read transaction.

• Data: This 16-bit field carries the data to/from the addressed PHY register

Table 35-6: MIIM Frame Format

As indicated previously, the size of an MIIM frame is 64 bits. However, the MIIM module may be

configured to suppress the preamble portion of the MII Management serial stream using the

Suppress Preamble bit (NOPRE) in the Ethernet Controller MAC MII Management Configuration

Refer to Clause 22 in the IEEE 802.3 Specification for more information on MIIM.

35.4.6.1 EXTERNAL PHY REGISTER ACCESS

The PHY registers provide configuration and control of the PHY module, and status information

about its operation. Unlike the on-chip SFRs, the PHY registers are not directly accessible

through the SFR control interface. Instead, access is accomplished through a special set of MAC

control registers that implement the Media Independent Interface Management. These control

registers are referred to as the MIIM registers. The PHY registers are accessed through the MIIM

interface of the MAC. To do this, the MII Management Command, Address, and Data registers in

the MAC must be used.

The registers that control access to the PHY registers are listed in Table 35-1, and include

Note: The Idle condition on MDIO is a high-impedance state.

Operation

Management Frame Fields

PRE PHYADST OPCODE REGAD TA DATA IDLE

READ 1….1 01 10 a0…a4 d0….d15r0…r4 Z0 Z

WRITE 1….1 01 01 a0…a4 d0….d15r0…r4 10 Z

Section 35. Ethernet Controller

35.4.6.5 SCANNING A PHY REGISTER

The MAC can be configured to perform automatic back-to-back read operations on a PHY

updates are desired.

To perform the scan operation, follow these steps:

1. Write the address of the PHY, and of the PHY register to be read from, into the

EMAC1MADR register.

2. Set the MII Management Scan Mode bit, SCAN (EMAC1MCMD<1>). The scan operation

begins and the MIIMBUSY bit is set.

3. The first read operation will complete after the first MIIM frame is transferred. Subsequent

reads will be done at the same interval until the operation is canceled. The MII

Management Read Data Not Valid bit, NOTVALID (EMAC1MIND<2>), may be polled to

determine when the first read operation is complete. Read the scanned register data from

the EMAC1MRDD register.

4. After setting the SCAN bit, the EMAC1MRDD register will be updated automatically every

MIIM frame interval. There is no status information, which can be used to determine when

the EMAC1MRDD register is updated.

5. When the MIIM scan operation is in progress, the software must not attempt to write to the

EMAC1MWTD register or start a read operation.

6. The MIIM scan operation can be cancelled by clearing the SCAN bit, and then polling the

MIIMBUSY bit. New operations may be started after the MIIMBUSY bit is cleared.

Example 35-1 provides example code for a MIIM initialization and PHY register read, write, and

scan.

Example 35-1: MIIM Initialization and PHY Access

// Assume we're running at 80 MHz and we're working with a PHY that supports a maximum

// 2.5 MHz MIIM frequency

#include <p32xxxx.h>

#define PHY_ADDRESS 0x1f // the address of the PHY

EMAC1MCFG=0x00008000; // issue reset

EMAC1MCFG=0; // clear reset

EMAC1MCFG=(0x8)<<2; // program the MIIM clock, divide by 40

// read the basic status PHY register: 1

unsigned int phyRegVal;

while(EMAC1MIND&0x1); // wait not busy

EMAC1MADR=0x1|((PHY_ADDRESS)<<8); // set the PHY and register address

EMAC1MCMD=1; // issue the read order

__asm__ __volatile__ (“nop; nop; nop;”); // wait busy to be set

while(EMAC1MIND&0x1); // wait op complete

EMAC1MCMD=0; // clear command register

phyRegVal=EMAC1MRDD; // read the selected register

// write the basic control PHY register: 0

while(EMAC1MIND&0x1); // wait in case of some previous operation

EMAC1MADR=0x0|((PHY_ADDRESS)<<8); // set the PHY and register address

EMAC1MWT=0x8000; // issue the write order (PHY reset)

__asm__ __volatile__ (“nop; nop; nop;”); // wait busy to be set

while(EMAC1MIND&0x1); // wait write complete

// Make sure data has been written

// Perform a scan of the status PHY register: 1

// Start the scan

while(EMAC1MIND&0x1); // wait in case of some previous operation

EMAC1MADR=0x1|((PHY_ADDRESS)<<8); // set the PHY and register address

EMAC1MCMD=0x2; // issue the scan order

// Read the status register

// Note that the read can occur now at any time

// without previously selecting the read operation and the register

while(EMAC1MIND&0x4); // wait data valid

phyRegVal=EMAC1MRDD; // read the scanned register

// After some time we decide to stop the scan operation

EMAC1MCMD=0; // cancel scan

Section 35. Ethernet Controller

Table 35-8: Ethernet Controller RX Buffer Descriptor Format

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Addr+0

———

BYTE_COUNT<10:0> U U U U U U U

— — — — — — —

Addr+4 DATA_BUFFER_ADDRESS<31:0>

Addr+8 RXF_RSV<7:0> U U U U U U U U PKT_CHECKSUM<15:0>

Addr+12 RSV<31:0>

Addr+16 NEXT_ED<31:0>

Note: The address of the Ethernet Descriptor must be 4-byte aligned.

Offset 0

bit 31 SOP: Start-of-Packet Enable bit

1 = Received a Start-of-Packet delimiter with this data buffer

0 = No Start-of-Packet delimiter present

bit 30 EOP: End-of-Packet Enable bit

1 = Transmit an End-of-Packet delimiter with this data buffer

0 = No End-of-Packet delimiter present

bit 29-27 Reserved: Maintain as ‘0’; ignore Read

bit 26-16 BYTE_COUNT<10:0>: Byte Count bits

The Byte Count represents the number of bytes to be transmitted for this descriptor. Valid

byte counts are 1-2047 per descriptor entry.

bit 15-9 User-defined bits; not used by the Ethernet Controller

bit 8 NPV: NEXT ED Pointer Valid Enable bit

1 = Next Descriptor is pointed to by the Next_ED field in this descriptor

0 = Next Descriptor follows this descriptor in system data memory

bit 7 EOWN: Ethernet Controller Own bit

(1)

1 = The Ethernet Controller owns the ED and its corresponding data buffer. The software

must not modify the ED or the data buffer.

0 = The software owns the ED and its corresponding data buffer. The Ethernet Controller

ignores all other fields in the ED.

Note: This bit can be written by either the software or the Ethernet Controller and it

must be initialized by the user application to the desired value prior to enabling

the Ethernet Controller.

bit 6-0 Reserved: Maintain as ‘0’; ignore Read

Offset 4

bit 31-0 DATA_BUFFER_ADDRESS<31:0>: Data Buffer Address bits

The starting point address of the Descriptor data buffer.

Offset 8

bit 31-24 RXF_RSV<7:0>: Receive Filter Status Vector bits

This field carries extra information about filtering of the received packet:

RXF_RSV<7> = Multicast match

RXF_RSV<6> = Broadcast match

RXF_RSV<5> = Unicast match

RXF_RSV<4> = Pattern Match match

RXF_RSV<3> = Magic Packet match

RXF_RSV<2> = Hash Table match

RXF_RSV<1> = NOT (Unicast match) AND NOT (Multicast Match)

RXF_RSV<0> = Runt packet

bit 23-16 User-defined bits; not used by the Ethernet Controller

bit 15-0 PKT_CHECKSUM<15:0>: The RX Packet Payload Checksum of this descriptor’s packet.

The calculated 1’s complement of the 16-bit packet checksum value.

PIC32 Family Reference Manual

35.4.9.4 ETHERNET TRANSMIT BUFFER MANAGEMENT

The Transmit Buffer Management (TXBM) block along with the TX DMA manages the flow of

transmit packets from the system memory to the MAC using the Transmit Buffer descriptors.

Transmit operation is enabled by setting the Transmit Request to Send bit, TXRTS

(ETHCON1<9>). In response to the TXRTS bit being set, the TX DMA will fetch an ED from the

EDT pointed to by the Ethernet Controller TX Packet Descriptor Start Address Register

(ETHTXST). After it has read the location of the data buffer and the control word for the data

buffer, the DMA will begin reading the data buffer data and writing it to the transmit port of the

MAC. If more than one descriptor is needed, the DMA will move to the next descriptor and will

continue sending data.

When a packet has to be transmitted from the system memory to the MAC, the packet data is

read from the memory pointed by the descriptor DATA_BUFFER_ADDRESS, see Figure 35-9.

The format of the transmitted packets is the same as the one for the received packets. Each

transmit packet buffer contains the standard Ethernet frame fields to be transmitted (DA, SA,

Type/Length, and Payload).

An example of a TX packet using three descriptors is illustrated in Figure 35-12. Once the

descriptor table entries and packet data buffers are programmed by the software, the transmit

operation is initiated by setting the TXRTS bit.

Note: Software must ensure that the TX descriptor list and the ETHTXST register are

initialized before setting the TXRTS bit.

Note: The EOWN bits in the transmitted descriptors should be set by the software starting

with the last descriptor of the packet to be transmitted and ending with the first. This

prevents any race condition between software and the Ethernet Controller

hardware.

PIC32 Family Reference Manual

Example 35-4: Ethernet Transmit Packet Code (Continued)

pEDcpt=pArrDcpt;

pBuff=pArrBuff;

pSize=pArrSize;

tailDcpt=0;

for(ix=0; ix< nArrayItems; ix++, pEDcpt++, pBuff++, pSize++)

{

// pass the descriptor to hw, use linked descriptors, set proper size

pEDcpt->pEDBuff=(unsigned char*)VA_TO_PA(pBuff); // set buffer

pEDcpt->hdr.w=0; // clear all the fields

pEDcpt-> hdr.NPV=1; // set next pointer valid

pEDcpt-> hdr.EOWN=1; // set hardware ownership

pEDcpt->hdr.bCount=* pSize; // set proper size

if(tailDcpt)

{

tailDcpt->next_ed=VA_TO_PA(&pEDcpt);

}

tailDcpt=pEDcpt;

}

// at this moment pEDcpt is an extra descriptor we use to end the descriptors list

pEDcpt->hdr.w=0; // software ownership

tailDcpt->next_ed= VA_TO_PA(&pEDcpt);

pArrDcpt[0].hdr.SOP=1; // Start-of-Packet

pArrDcpt[nArrayItems-1].hdr.EOP=1; // End-of-Packet

ETHTXST=VA_TO_PA(pArrDcpt); // set the transmit address

ETHCON1SET= 0x00008200; // set the ON and the TXRTS

// the ETHC will transmit the buffers we just programmed

/* do something else in between */

while(!(ETHCON1&0x00000200)); // wait transmission to be done

// check the ETHSTAT register to see the transfer result

Note: Example 35-4 uses the syntax specific to the MPLAB

C Compiler for PIC32 MCUs.

Refer to your compiler manual regarding support for packed data structures.

PIC32 Family Reference Manual

Example 35-5: Ethernet Receive Packet Code (Continued)

35.4.10 Ethernet Initialization Sequence

To initialize the Ethernet Controller to receive and transmit Ethernet messages, perform these

steps:

1. Ethernet Controller Initialization:

a) Disable Ethernet interrupts in the EVIC register by clearing the Ethernet Controller IE

bit, ETHIE (IEC1<28>).

b) Turn the Ethernet Controller off, and then clear the ON bit (ETHCON1<15>), the

RXEN bit (ETHCON1<8>), and the TXRTS bit (ETHCON1<9>).

c) Abort the Wait activity by polling the ETHBUSY bit (ETHSTAT<7>).

d) Clear the Ethernet Interrupt Flag bit (ETHIF) in the Interrupts module (IFS1<28>).

e) Disable any Ethernet Controller interrupt generation by clearing the ETHIRQIE

f) Clear the TX and RX start addresses from the ETHTXST and ETHRXST registers.

2. MAC Initialization:

a) Reset the MAC using the SOFTRESET bit (EMAC1CFG1<15>), or individually reset

the modules by setting the Reset MCS/RX bit, RESETRMCS (EMAC1CFG1<11), the

Reset RX Function bit, RESETRFUN (EMAC1CFG1<10>), the Reset MCS/TX bit,

RESETTMCS (EMAC1CFG1<9>), and the Reset TX Function bit, RESETTFUN

(EMAC1CFG1<8>).

b) Use the Configuration bit setting, FETHIO (DEVCFG3<25>), to detect the alternate

or default I/O configuration. Refer to Section 32. “Configuration” (DS60001124) for

more information.

c) Use the Configuration bit setting, FMIIEN (DEVCFG3<24>), to detect MII/RMII

operation mode.

d) Initialize as digital, all of the pins used by the MAC PHY interface (generally, only

those pins that have shared analog functionality need to be configured).

e) Initialize the MIIM interface:

i. If the RMII operation is selected, Reset the RMII module by using the

RESETRMII bit (EMAC1SUPP<11>) and set proper speed in the SPEEDRMII bit

(EMAC1SUPP<8>).

ii. Issue an MIIM block reset, by setting and then clearing the Test Reset MII

Management bit, RESETMGMT (EMAC1MCFG<15>).

iii. Select a proper divider in the CLKSEL<3:0> bits (EMAC1MCFG<5:2>) for the

MIIM PHY communication based on the system running clock frequency and the

external PHY supported clock.

tailDcpt=pEDcpt;

}

// at this moment pEDcpt is an extra descriptor we use to end the descriptors list

pEDcpt->hdr.w=0; // software ownership

tailDcpt->next_ed= VA_TO_PA(&pEDcpt);

ETHRXST=VA_TO_PA(pArrDcpt); // set the address of the first RX descriptor

ETHCON1SET= 0x00008100; // set the ON and the RXEN

// the Ethernet Controller will receive frames and place them in the receive buffers

// we just programmed

/* do something else in between */

// can check the BUFCNT (ETHSTAT<16:23>) or RXDONE (ETHIRQ<7>)

// to see if there are packets received

Note: Example 35-5 uses the syntax specific to the MPLAB C Compiler for PIC32 MCUs.

Refer to your compiler manual regarding support for packed data structures.

PIC32 Family Reference Manual

35.5 ETHERNET INTERRUPTS

The PIC32 device can generate interrupts reflecting the events that occur during the Ethernet

Controller’s transfer of frames. Each of the Ethernet Controller interrupt events has a

corresponding Interrupt Enable bit (IE) in the ETHIEN register, which must be set for an interrupt

to be generated. However, regardless of the value of the ETHIEN register, the status of all

interrupt events is directly readable through the ETHIRQ register. Therefore, the software has

visibility of an event generating a potential interrupt by polling the register, and not having an

interrupt propagate out of the Ethernet module.

Ethernet interrupts are persistent. This means that as long as the event that generated the

interrupt is pending, the interrupt signal from the Ethernet Controller module will remain asserted.

Following is a description of the interrupt events generated by the transmission and receive of

Ethernet frames.

Transmit path related interrupt events:

• TX DMA engine transfer error interrupt, signaled by the TXBUSE bit (ETHIRQ<14>) and

enabled using the TXBUSEIE bit (ETHIEN<14>). This event occurs when the TX DMA

encounters a bus error during a memory access, and is caused by an addressing error

(usually because of a bad pointer).

• Transmission done interrupt, signaled by the TXDONE bit (ETHIRQ<3>) and enabled using

the TXDONEIE bit (ETHIEN<3>). This event occurs when the currently transmitted TX

packet completes transmission and the TSV is loaded into the first descriptor of the packet.

• Transmission aborted interrupt, signaled by the TXABORT bit (ETHIRQ<2>) and enabled

using the TXABORTIE bit (ETHIEN<2>). This event occurs when the MAC aborts the

transmission due to one of these reasons:

- Jumbo TX packet abort (packet size is greater than the maximum size MACMAXF bit

(EMAC1MAXF<15:0>))

- Underrun abort (Transmit engine cannot keep up with the requested data flow. This

happens when the system bus is overloaded.)

- Excessive defer abort (Packet was deferred in excess of 6071 nibble times in

100 Mbps mode or 24,287 bit times in 10 Mbps mode)

- Late collision abort (Collision occurred beyond the collision window)

- Excessive collisions abort (Packet was aborted because the number of collisions

exceeded the RETX bit (EMAC1CLRT<3:0>)

Receive path related interrupt events:

• RX DMA engine transfer error interrupt, signaled by the RXBUSE bit (ETHIRQ<13>) and

enabled using the RXBUSEIE bit (ETHIEN<13>). This event occurs when the RX DMA

encounters a bus error during a memory access and is caused by an addressing error

(usually because of a bad pointer).

• Receive done interrupt, signaled by the RXDONE bit (ETHIRQ<7>) and enabled using the

RXDONEIE bit (ETHIEN<7>). This event occurs whenever a packet is successfully

received.

• Packet pending interrupt, signaled by the PKTPEND bit (ETHIRQ<6>) and enabled using the

PKTPENDIE bit (ETHIEN<6>). This event occurs whenever the buffer counter

BUFCNT<7:0> bits (ETHSTAT<23:16>) has a value greater than ‘0’.

• Receive activity interrupt, signaled by the RXACT bit (ETHIRQ<5>) and enabled using the

RXACTIE bit (ETHIEN<5>). This event occurs whenever data is stored in the RX BM FIFO.

• Receive buffer not available interrupt, signaled by the RXBUFNA bit (ETHIRQ<1>) and

enabled using the RXBUFNAIE bit (ETHIEN<1>). This event occurs whenever the RX

DMA runs out of descriptors by fetching a descriptor not owned by hardware (EOWN = 0).

Note: An early collision will cause the MAC to assert the Retry, but not the Abort. This

condition will therefore not cause an interrupt.

PIC32 Family Reference Manual

35.5.1 Interrupt Configuration

The Ethernet Controller module has multiple internal interrupt flags (TXBUSE, RXBUSE,

EWMARK, FWMARK, RXDONE, PKTPEND, RXACT, TXDONE, TXABORT, RXBUFNA and

RXOVFLW) and corresponding enable interrupt control bits (TXBUSEIE, RXBUSEIE,

EWMARKIE, FWMARKIE, RXDONEIE, PKTPENDIE, RXACTIE, TXDONEIE, TXABORTIE,

RXBUFNAIE and RXOVFLIE). However, for the interrupt controller, there is one dedicated

interrupt flag bit for the Ethernet Controller, ETHIF (IFS1<28>), and the corresponding interrupt

enable/mask bit, ETHIE (IEC1<28>).

The Ethernet Controller module has its own priority and sub-priority levels independent of other

peripherals. The ETHIF bit (IFS1<28>) will be set without regard to the state of the corresponding

enable bit, ETHIE (IEC1<28>). The ETHIF can be polled by software, if required.

The ETHIE bit (IEC1<28>) is used to define the behavior of the Vector Interrupt Controller (INT)

module when the corresponding ETHIF bit is set. When the corresponding ETHIE bit is clear, the

Interrupts module does not generate a CPU interrupt for the event. If the ETHIE bit is set, the

Interrupts module will generate an interrupt to the CPU when the ETHIF bit is set (subject to the

priority and sub-priority as follows). It is the responsibility of the user software routine that

services a particular interrupt to clear the interrupt flag bit before the service routine is complete.

The priority of the Ethernet Controller module interrupt can be set using the IPC12 register of the

INT controller. This priority defines the priority group to which the interrupt source will be

assigned. The priority groups range from a value of 7 (the highest priority) to a value of 0, which

does not generate an interrupt. An interrupt being serviced will be preempted by an interrupt in

a higher priority group.

The sub-priority bits allow setting the priority of an interrupt source within a priority group. The

values for the sub-priority range from 3 (highest priority) to 0 (lowest priority). An interrupt with

the same priority group but having a higher sub-priority value will not preempt a lower sub-priority

interrupt that is in progress.

The priority group and sub-priority bits allow more than one interrupt source to share the same

priority and sub-priority. If simultaneous interrupts occur in this configuration, the natural order

of the interrupt sources within a priority/sub-priority group pair determine the interrupt

generated.

The natural priority is based on the vector numbers of the interrupt sources. The lower the vector

number, the higher the natural priority of the interrupt. Any interrupts that were overridden by

natural order will then generate their respective interrupts based on priority, sub-priority and

natural order after the interrupt flag for the current interrupt is cleared.

After an enabled interrupt is generated, the CPU will jump to the vector assigned to that interrupt.

The vector number for the interrupt is the same as the natural order number. The CPU will then

begin executing code at the vector address. The user’s code at this vector address should

perform any application specific operations and clear the ETHIF interrupt flags (as well as the

corresponding event in the ETHIRQ register, if a software clearable interrupt) and then exit. Refer

to the vector address table in Section 8. “Interrupts” (DS60001108) for more information.

Table 35-9 provides the Ethernet interrupt vectors for various offsets with Ebase = 0x8000:0000.

Example 35-6 shows the Ethernet initialization with interrupts enabled code.

Table 35-9: Ethernet Interrupt Vectors for Various Offsets with EBASE = 0x8000:0000

Note: All of the interrupt conditions for the Ethernet Controller module share one interrupt

vector.

Interrupt

Vector/

Natural

Order

IRQ

Number

Vector

Address

IntCtl.VS

= 0x01

Vector

Address

IntCtl.VS

= 0x02

Vector

Address

IntCtl.VS

= 0x04

Vector

Address

IntCtl.VS

= 0x08

Vector

Address

IntCtl.VS

= 0x10

ETH 48 60 8000 0800 8000 0e00 8000 1a00 8000 3200 8000 6200

PIC32 Family Reference Manual

35.9 RELATED APPLICATION NOTES

This section lists application notes that are related to this section of the manual. These

application notes may not be written specifically for the PIC32 device family, but the concepts are

pertinent and could be used with modification and possible limitations. The current application

notes related to Ethernet Controller module are:

Title Application Note #

Ethernet Theory of Operation AN1120

Note: Please visit the Microchip web site (www.microchip.com) for additional application

notes and code examples for the PIC32 family of devices.

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