Microchip PIC32MZ1024EFE064 Manual
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PIC32MZ1024EFE064
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© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-1
Section 22. 12-bit High-Speed Successive Approximation
Register (SAR) Analog-to-Digital Converter (ADC)
This section of the manual contains the following major topics:
22.1 Introduction .................................................................................................................. 22-2
22.2 Control Registers ......................................................................................................... 22-6
22.3 ADC Operation........................................................................................................... 22-61
22.4 ADC Module Configuration ........................................................................................ 22-65
22.5 Additional ADC Functions .......................................................................................... 22-85
22.6 Interrupts.................................................................................................................. 22-108
22.7 Operation During Power-Saving Modes .................................................................. 22-114
22.8 Effects of Reset........................................................................................................ 22-116
22.9 Transfer Function..................................................................................................... 22-116
22.10 ADC Sampling Requirements.................................................................................. 22-117
22.11 Connection Considerations...................................................................................... 22-117
22.12 Related Application Notes........................................................................................ 22-118
22.13 Revision History ....................................................................................................... 22-119
PIC32 Family Reference Manual
DS60001344E-page 22-2 © 2015-2019 Microchip Technology Inc.
22.1 INTRODUCTION
The PIC32 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital
Converter (ADC) includes the following features:
• 12-bit resolution
• Up to eight ADC modules with dedicated Sample and Hold (S&H) circuits (see Note 1)
• Two dedicated ADC modules can be combined in Turbo mode to provide double
conversion rate
• Single-ended and/or differential inputs
• Can operate during Sleep mode
• Supports touch sense applications
• Up to six digital comparators
• Up to six digital filters supporting two modes:
- Oversampling mode
- Averaging mode
• FIFO and DMA engine for dedicated ADC modules (see Note 2)
• Early interrupt generation resulting in faster processing of converted data
• Designed for motor control, power conversion, and general purpose applications
The dedicated ADC modules use a single input (or its alternate) and is intended for high-speed
and precise sampling of time-sensitive or transient inputs, whereas the shared ADC module
incorporates a multiplexer on the input to facilitate a larger group of inputs, with slower sampling,
and provides flexible automated scanning option through the input scan logic.
For each ADC module, the analog inputs are connected to the S&H capacitor. The clock,
sampling time, and output data resolution for each ADC module can be set independently. The
ADC module performs the conversion of the input analog signal based on the configurations set
in the registers. When conversion is complete, the final result is stored in the result buffer for the
specific analog input and is passed to the digital filter and digital comparator if configured to use
data from this particular sample.
A simplified block diagram of the ADC module is illustrated in Figure 22-1.
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device, this manual section may not apply to all
PIC32 devices.
Please refer to the note at the beginning of the “ADC” chapter in the current device
data sheet to check whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
Note 1: Depending on the device, the 12-bit High-Speed SAR ADC has up to seven
dedicated ADC modules and one shared ADC module. Throughout this chapter,
the diagrams and code examples refer to a device with seven dedicated ADC
modules (ADC0-ADC6) and one shared ADC (ADC7). Please consult the “ADC”
chapter in the specific device data sheet to determine which ADC modules are
available for your device.
2: This feature is not available on all devices. Refer to the “ADC” chapter in the
specific device data sheet to determine availability.
3: Prior to enabling the ADC module, the user application must copy the ADC
calibration data (DEVADCx) from the Configuration memory into the ADC
Configuration registers (ADC0CFG-ADC7CFG). Refer to the “ADC” chapter in the
specific device data sheet for more information.
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-3
Section 22. 12-bit High-Speed SAR ADC
Figure 22-1: ADC Block Diagram
Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features
are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the
actual ANx selections, ADC module availability, and the specific FIFO and DMA features.
ADC0
ADC7
AV
DD
AV
SS
V
REF
+ V
REF
-
VREFSEL<2:0>
V
REFH
V
REFL
ADCSEL<1:0>
CONCLKDIV<5:0>
T
CY
FRC PBCLK
T
Q
ADCDIV<6:0>
(ADCxTIME<22:16>)
ADCDIV<6:0>
(ADCCON2<6:0>)
T
AD0
-T
AD6
T
AD7
ADDATA0
…...
ADDATA63
(Dedicated
ADC)
(Dedicated
ADC)
FIFO
DMA
Digital Filter
Digital Comparator Interrupt/Event
Capacitive Voltage
Divider (CVD) Interrupt/Event
Triggers,
Turbo Channel,
Scan Control Logic
Trigger
Status and Control
Registers
ADC6
SH0ALT<1:0>
(ADCTRGMODE<17:16>)
ANx
V
REFL
0
1
DIFFx<1>
(ADCIMCONx<x>)
ANa
AN1
V
REFL
0
1
DIFF1<1>
(ADCIMCON1<3>)
SH6ALT<1:0>
(ADCTRGMODE<29:28>)
ANx
V
REFL
0
1
DIFFx<1>
(ADCIMCONx<x>)
AN49
IV
CTMU
IV
BAT
AN48
AN7
CVD
Capacitor
T
CLK
ANb
ANc
ANd
00
01
10
11
ANb
ANc
ANd
00
01
10
11
SYSTEMBUS
ANa
Interrupt
Data
PIC32 Family Reference Manual
DS60001344E-page 22-4 © 2015-2019 Microchip Technology Inc.
Figure 22-2: FIFO Block Diagram
FEN
(ADCFSTAT<31>
FIFO
(Depth Device Dependent)
ADCFIFO DATA<31:0>
ADCID<2:0>
ADCFSTAT<2:0> ADCx ID
ADCx ID Converted Data
ADC6
ADC6EN
(ADCFSTAT<30>)
ADC5
ADC5EN
(ADCFSTAT<29>)
ADC0
ADC0EN
(ADCFSTAT<24>)
If data
available in
FIFO
FRDY
ADCFSTAT<22>
FIEN
(ADCFSTAT<23>
Interrupt
FCNT<7:0>
ADCFSTAT<15:8>
(Number of data in FIFO)
Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features
are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the
actual ANx selections, ADC module availability, and the specific FIFO and DMA features.
PIC32 Family Reference Manual
DS60001344E-page 22-10 © 2015-2019 Microchip Technology Inc.
Register 22-1: ADCCON1: ADC Control Register 1
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRBEN TRBERR TRBMST<2:0> TRBSLV<2:0>
23:16
R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FRACT SELRES<1:0> STRGSRC<4:0>
15:8
R/W-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 U-0
ON — SIDL AICPMPEN CVDEN FSSCLKEN FSPBCLKEN —
7:0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— IRQVS<2:0> STRGLVL DMABL<2:0>
Legend: HC = Hardware Set HS = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 TRBEN: Turbo Channel Enable bit
1 = Enable the Turbo channel
0 = Disable the Turbo channel
bit 30 TRBERR: Turbo Channel Error Status bit
1 = An error occurred while setting the Turbo channel and Turbo channel function to be disabled regardless
of the TRBEN bit being set to ‘1’.
0 = Turbo channel error did not occur
Note: The status of this bit is valid only after the TRBEN bit is set.
bit 29-27 TRBMST<2:0>: Turbo Master ADCx bits
111 = Reserved
110 = ADC6 is selected as the Turbo Master
•
•
•
000 = ADC0 is selected as the Turbo Master
bit 26-24 TRBSLV<2:0>: Turbo Slave ADCx bits
111 = Reserved
110 = ADC6 is selected as the Turbo Slave
•
•
•
000 = ADC0 is selected as the Turbo Slave
bit 23 FRACT: Fractional Data Output Format bit
1 = Fractional
0 = Integer
bit 22-21 SELRES<1:0>: Shared ADC Resolution bits
11 = 12 bits (default)
10 = 10 bits
01 = 8 bits
00 = 6 bits
bit 20-16 STRGSRC<4:0>: Scan Trigger Source Select bits
11111 00100 - = Refer to the “ADC” chapter in the specific device data sheet for trigger source selections
00011 = Reserved
00010 = Global level software trigger (GLSWTRG) is not self-cleared
00001 = Global software trigger (GSWTRG) is self-cleared on the next clock cycle
00000 = No trigger
bit 15 ON: ADC Module Enable bit
1 = ADC module is enabled
0 = ADC module is disabled
Note: The ON bit should be set only after the ADC module has been configured.
bit 14 Unimplemented: Read as ‘0’
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-11
Section 22. 12-bit High-Speed SAR ADC
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation in Idle mode
bit 12 AICPMPEN: Analog Input Charge Pump Enable bit
1 = Analog input charge pump is enabled (default)
0 = Analog input charge pump is disabled
bit 11 CVDEN: Capacitive Voltage Division Enable bit
1 = CVD operation is enabled
0 = CVD operation is disabled
bit 10 FSSCLKEN: Fast Synchronous System Clock to ADC Control Clock bit
1 = Fast synchronous system clock to ADC control clock is enabled
0 = Fast synchronous system clock to ADC control clock is disabled
bit 9 FSPBCLKEN: Fast Synchronous Peripheral Clock to ADC Control Clock bit
1 = Fast synchronous peripheral clock to ADC control clock is enabled
0 = Fast synchronous peripheral clock to ADC control clock is disabled
bit 8-7 Unimplemented: Read as ‘0’
bit 6-4 IRQVS<2:0>: Interrupt Vector Shift bits
To determine interrupt vector address, this bit specifies the amount of left shift done to the ARDYx status
bits in the ADCDSTAT1 and ADCDSTAT2 registers, prior to adding with the ADCBASE register (see
22.6.2 “ADC Base Register (ADCBASE) Usage” for more information).
Interrupt Vector Address = Read Value of ADCBASE = Value written to ADCBASE + x << IRQVS<2:0>,
where ‘x’ is the smallest active input ID from the ADCDSTAT1 or ADCDSTAT2 registers (which has highest
priority).
111 = Shift x left 7 bit position
110 = Shift x left 6 bit position
101 = Shift x left 5 bit position
100 = Shift x left 4 bit position
011 = Shift x left 3 bit position
010 = Shift x left 2 bit position
001 = Shift x left 1 bit position
000 = Shift x left 0 bit position
bit 3 STRGLVL: Scan Trigger High Level/Positive Edge Sensitivity bit
1= Scan trigger is high level sensitive. Once STRIG mode is selected (TRGSRCx<4:0> in the ADCTRGx
register), the scan trigger will continue for all selected analog inputs, until the STRIG option is removed.
0= Scan trigger is positive edge sensitive. Once STRIG mode is selected (TRGSRCx<4:0> in the
ADCTRGx register), only a single scan trigger will be generated, which will complete the scan of all
selected analog inputs.
bit 2-0 DMABL<2:0>: DMA Buffer Length Size bits
111 = Allocates 128 locations in RAM to each analog input
110 = Allocates 64 locations in RAM to each analog input
101 = Allocates 32 locations in RAM to each analog input
100 = Allocates 16 locations in RAM to each analog input
011 = Allocates 8 locations in RAM to each analog input
010 = Allocates 4 locations in RAM to each analog input
001 = Allocates 2 locations in RAM to each analog input
000 = Allocates 1 location in RAM to each analog input
Note: Since each output data is 16-bit wide, one location consists of 2 bytes.
Register 22-1: ADCCON1: ADC Control Register 1 (Continued)
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-13
Section 22. 12-bit High-Speed SAR ADC
bit 14 REFFLTIEN: Band Gap/V
REF
Voltage Fault Interrupt Enable bit
1 = Interrupt will be generated when the REFFLT bit is set
0 = No interrupt is generated when the REFFLT bit is set
bit 13 EOSIEN: End of Scan Interrupt Enable bit
1 = Interrupt will be generated when EOSRDY bit is set
0 = No interrupt is generated when the EOSRDY bit is set
bit 12 ADCEIOVR: Early Interrupt Request Override bit
1 = Early interrupt generation is overridden and interrupt generation is controlled by the ADCGIRQEN1
and ADCGIRQEN2 registers
0 = Early interrupt generation is not overridden and interrupt generation is controlled by the ADCEIEN1
and ADCEIEN2 registers
bit 11 ECRIEN: External Conversion Request Interface Enable bit
1 = Enables ADC conversion start from external module (such as PTG)
0 = External modules cannot start ADC conversion
bit 10-8 ADCEIS<2:0>: Shared ADC Early Interrupt Select bits
These bits select the number of clocks (T
AD
)
prior to the arrival of valid data that the associated interrupt
is generated.
111 = The data ready interrupt is generated 8 ADC clocks prior to end of conversion
110 = The data ready interrupt is generated 7 ADC clocks prior to end of conversion
•
•
•
001 = The data ready interrupt is generated 2 ADC module clocks prior to end of conversion
000 = The data ready interrupt is generated 1 ADC module clock prior to end of conversion
Note: All options are available when the selected resolution, set by the SELRES<1:0> bits
(ADCCON1<22:21>), is 12-bit or 10-bit. For a selected resolution of 8-bit, options from ‘000’ to
‘101’ are valid. For a selected resolution of 6-bit, options from ‘000’ to ‘011’ are valid.
bit 7 Unimplemented: Read as ‘0’
bit 6-0 ADCDIV<6:0>: Shared ADC Clock Divider bits
1111111 = 254 * T
Q
= T
AD
•
•
•
0000011 = 6 * T
Q
= T
AD
0000010 = 4 * T
Q
= T
AD
0000001 = 2 * T
Q
= T
AD
0000000 = Reserved
The ADCDIV<6:0> bits divide the ADC control clock (T
Q
) to generate the clock for the Shared ADC (T
AD
).
Register 22-2: ADCCON2: ADC Control Register 2 (Continued)
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-15
Section 22. 12-bit High-Speed SAR ADC
bit 19 DIGEN3: ADC3 Digital Enable bit
(5)
1 = ADC3 is digital enabled
0 = ADC3 is digital disabled
bit 18 DIGEN2: ADC2 Digital Enable bit
(5)
1 = ADC2 is digital enabled
0 = ADC2 is digital disabled
bit 17 DIGEN1: ADC1 Digital Enable bit
(5)
1 = ADC1 is digital enabled
0 = ADC1 is digital disabled
bit 16 DIGEN0: ADC0 Digital Enable bit
(5)
1 = ADC0 is digital enabled
0 = ADC0 is digital disabled
bit 15-13 VREFSEL<2:0>: Voltage Reference (V
REF
) Input Selection bits
bit 12 TRGSUSP: Trigger Suspend bit
1 = Triggers are blocked from starting a new analog-to-digital conversion, but the ADC module is not disabled
0 = Triggers are not blocked
bit 11 UPDIEN: Update Ready Interrupt Enable bit
1 = Interrupt will be generated when the UPDRDY bit is set by hardware
0 = No interrupt is generated
bit 10 UPDRDY: ADC Update Ready Status bit
1 = ADC SFRs can be updated
0 = ADC SFRs cannot be updated
Note: This bit is only active while the TRGSUSP bit is set and there are no more running conversions of
any ADC modules.
bit 9 SAMP: Class 2 and Class 3 Analog Input Sampling Enable bit
(1,2,3,4)
1 = The ADC S&H amplifier is sampling
0 = The ADC S&H amplifier is holding
Register 22-3: ADCCON3: ADC Control Register 3 (Continued)
Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the
bit is cleared. Also, usage of the SAMP bit will cause settings of the SAMC<9:0> bits (ADCCON2<25:16>)
to be ignored.
2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC. All Class 1 analog
inputs are not affected by the SAMP bit.
3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit
and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits and
STRGSRC<4:0> bits should be set to ‘00000’ to disable all external hardware triggers and prevent them
from interfering with the software-controlled sampling command signal SAMP and with the
software-controlled trigger RQCNVRT.
5: Depending on the device, the function will vary. Refer to the “ADC” chapter in the specific device data
sheet to determine the function that is available for your device.
VREFSEL<2:0> AD
REF
+ AD
REF
-
111 AV
DD
Internal V
REFL
110 Internal V
REFH
AV
SS
101 Internal V
REFH
External V
REFL
100 Internal V
REFH
Internal V
REFL
011 External V
REFH
External V
REFL
010 AV
DD
External V
REFL
001 External V
REFH
AVss
000 AV
DD
AVss
PIC32 Family Reference Manual
DS60001344E-page 22-16 © 2015-2019 Microchip Technology Inc.
bit 8 RQCNVRT: Individual ADC Input Conversion Request bit
This bit and its associated ADINSEL<5:0> bits enable the user to individually request an analog-to-digital
conversion of an analog input through software.
1 = Trigger the conversion of the selected ADC input as specified by the ADINSEL<5:0> bits
0 = Do not trigger the conversion
Note: This bit is automatically cleared in the next ADC clock cycle.
bit 7 GLSWTRG: Global Level Software Trigger bit
1 = Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal, either
through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0>
bits in the ADCCON1 register
0 = Do not trigger an analog-to-digital conversion
bit 6 GSWTRG: Global Software Trigger bit
1 = Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal, either
through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0>
bits in the ADCCON1 register
0 = Do not trigger an analog-to-digital conversion
Note: This bit is automatically cleared in the next ADC clock cycle.
bit 5-0 ADINSEL<5:0>: Analog Input Select bits
(5)
These bits select the analog input to be converted when the RQCNVRT bit is set, where, MAX_AN_INPUT
is the maximum analog inputs available on the device.
MAX_AN_INPUT + 4 = Device dependent (see Note 5)
MAX_AN_INPUT + 3 = Device dependent (see Note 5)
MAX_AN_INPUT + 2 = Device dependent (see Note 5)
MAX_AN_INPUT + 1 = Device dependent (see Note 5)
MAX_AN_INPUT = AN[MAX_AN_INPUT]
•
•
•
000001 = AN1
000000 = AN0
Register 22-3: ADCCON3: ADC Control Register 3 (Continued)
Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the
bit is cleared. Also, usage of the SAMP bit will cause settings of the SAMC<9:0> bits (ADCCON2<25:16>)
to be ignored.
2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC. All Class 1 analog
inputs are not affected by the SAMP bit.
3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit
and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits and
STRGSRC<4:0> bits should be set to ‘00000’ to disable all external hardware triggers and prevent them
from interfering with the software-controlled sampling command signal SAMP and with the
software-controlled trigger RQCNVRT.
5: Depending on the device, the function will vary. Refer to the “ADC” chapter in the specific device data
sheet to determine the function that is available for your device.
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-17
Section 22. 12-bit High-Speed SAR ADC
Register 22-4: ADCTRGMODE: ADC Triggering Mode for Dedicated ADC Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — SH6ALT<1:0> SH5ALT<1:0> SH4ALT<1:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SH3ALT<1:0> SH2ALT<1:0> SH1ALT<1:0> SH0ALT<1:0>
15:8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— STRGEN6 STRGEN5 STRGEN4 STRGEN3 STRGEN2 STRGEN1 STRGEN0
7:0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SSAMPEN6 SSAMPEN5 SSAMPEN4 SSAMPEN3 SSAMPEN2 SSAMPEN1 SSAMPEN0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘ ’
bit 29-28 SH6ALT<1:0>: ADC6 Analog Input Select bit
11 01 - = Refer to the “ADC” chapter in the specific device data sheet for the available selections
00 = AN6
bit 27-26 SH5ALT<1:0>: ADC5 Analog Input Select bit
11 01 - = Refer to the “ADC” chapter in the specific device data sheet for the available selections
00 = AN5
bit 25-24 SH4ALT<1:0>: ADC4 Analog Input Select bit
11 01 - = Refer to the “ADC” chapter in the specific device data sheet for the available selections
00 = AN4
bit 23-22 SH3ALT<1:0>: ADC3 Analog Input Select bit
11 01 - = Refer to the “ADC” chapter in the specific device data sheet for the available selections
00 = AN3
bit 21-20 SH2ALT<1:0>: ADC2 Analog Input Select bit
11 01 - = Refer to the “ADC” chapter in the specific device data sheet for the available selections
00 = AN2
bit 19-18 SH1ALT<1:0>: ADC1 Analog Input Select bit
11 01 - = Refer to the “ADC” chapter in the specific device data sheet for the available selections
00 = AN1
bit 17-16 SH0ALT<1:0>: ADC0 Analog Input Select bit
11 01 - = Refer to the “ADC” chapter in the specific device data sheet for the available selections
00 = AN0
bit 15 Unimplemented: Read as ‘ ’
bit 14 STRGEN6: ADC6 Presynchronized Triggers bit
1 = ADC6 uses presynchronized triggers
0 = ADC6 does not use presynchronized triggers
bit 13 STRGEN5: ADC5 Presynchronized Triggers bit
1 = ADC5 uses presynchronized triggers
0 = ADC5 does not use presynchronized triggers
bit 12 STRGEN4: ADC4 Presynchronized Triggers bit
1 = ADC4 uses presynchronized triggers
0 = ADC4 does not use presynchronized triggers
bit 11 STRGEN3: ADC3 Presynchronized Triggers bit
1 = ADC3 uses presynchronized triggers
0 = ADC3 does not use presynchronized triggers
PIC32 Family Reference Manual
DS60001344E-page 22-18 © 2015-2019 Microchip Technology Inc.
bit 10 STRGEN2: ADC2 Presynchronized Triggers bit
1 = ADC2 uses presynchronized triggers
0 = ADC2 does not use presynchronized triggers
bit 9 STRGEN1: ADC1 Presynchronized Triggers bit
1 = ADC1 uses presynchronized triggers
0 = ADC1 does not use presynchronized triggers
bit 8 STRGEN0: ADC0 Presynchronized Triggers bit
1 = ADC0 uses presynchronized triggers
0 = ADC0 does not use presynchronized triggers
bit 7 Unimplemented: Read as ‘ ’
bit 6 SSAMPEN6: ADC6 Synchronous Sampling bit
1 = ADC6 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC6 does not use synchronous sampling
bit 5 SSAMPEN5: ADC5 Synchronous Sampling bit
1 = ADC5 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC5 does not use synchronous sampling
bit 4 SSAMPEN4: ADC4 Synchronous Sampling bit
1 = ADC4 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC4 does not use synchronous sampling
bit 3 SSAMPEN3: ADC3 Synchronous Sampling bit
1 = ADC3 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC3 does not use synchronous sampling
bit 2 SSAMPEN2: ADC2Synchronous Sampling bit
1 = ADC2 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC2 does not use synchronous sampling
bit 1 SSAMPEN1: ADC1 Synchronous Sampling bit
1 = ADC1 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC1 does not use synchronous sampling
bit 0 SSAMPEN0: ADC0 Synchronous Sampling bit
1 = ADC0 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC0 does not use synchronous sampling
Register 22-4: ADCTRGMODE: ADC Triggering Mode for Dedicated ADC Register (Continued)
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-19
Section 22. 12-bit High-Speed SAR ADC
Register 22-5: ADCIMCON1: ADC Input Mode Control Register 1
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF15 SIGN15 DIFF14 SIGN14 DIFF13 SIGN13 DIFF12 SIGN12
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF11 SIGN11 DIFF10 SIGN10 DIFF9 SIGN9 DIFF8 SIGN8
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF7 SIGN7 DIFF6 SIGN6 DIFF5 SIGN5 DIFF4 SIGN4
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF3 SIGN3 DIFF2 SIGN2 DIFF1 SIGN1 DIFF0 SIGN0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 DIFF15: AN15 Mode bit
1 = AN15 is using Differential mode
0 = AN15 is using Single-ended mode
bit 30 SIGN:15 AN15 Signed Data Mode bit
1 = AN15 is using Signed Data mode
0 = AN15 is using Unsigned Data mode
bit 29 DIFF14: AN14 Mode bit
1 = AN14 is using Differential mode
0 = AN14 is using Single-ended mode
bit 28 SIGN14: AN14 Signed Data Mode bit
1 = AN14 is using Signed Data mode
0 = AN14 is using Unsigned Data mode
bit 27 DIFF13: AN13 Mode bit
1 = AN13 is using Differential mode
0 = AN13 is using Single-ended mode
bit 26 SIGN13: AN13 Signed Data Mode bit
1 = AN13 is using Signed Data mode
0 = AN13 is using Unsigned Data mode
bit 25 DIFF12: AN12 Mode bit
1 = AN12 is using Differential mode
0 = AN12 is using Single-ended mode
bit 24 SIGN12: AN12 Signed Data Mode bit
1 = AN12 is using Signed Data mode
0 = AN12 is using Unsigned Data mode
bit 23 DIFF11: AN11 Mode bit
1 = AN11 is using Differential mode
0 = AN11 is using Single-ended mode
bit 22 SIGN11: AN11 Signed Data Mode bit
1 = AN11 is using Signed Data mode
0 = AN11 is using Unsigned Data mode
bit 21 DIFF10: AN10 Mode bit
1 = AN10 is using Differential mode
0 = AN10 is using Single-ended mode
PIC32 Family Reference Manual
DS60001344E-page 22-20 © 2015-2019 Microchip Technology Inc.
bit 20 SIGN10: AN10 Signed Data Mode bit
1 = AN10 is using Signed Data mode
0 = AN10 is using Unsigned Data mode
bit 19 DIFF9: AN9 Mode bit
1 = AN9 is using Differential mode
0 = AN9 is using Single-ended mode
bit 18 SIGN9: AN9 Signed Data Mode bit
1 = AN9 is using Signed Data mode
0 = AN9 is using Unsigned Data mode
bit 17 DIFF8: AN 8 Mode bit
1 = AN8 is using Differential mode
0 = AN8 is using Single-ended mode
bit 16 SIGN8: AN8 Signed Data Mode bit
1 = AN8 is using Signed Data mode
0 = AN8 is using Unsigned Data mode
bit 15 DIFF7: AN7 Mode bit
1 = AN7 is using Differential mode
0 = AN7 is using Single-ended mode
bit 14 SIGN7: AN7 Signed Data Mode bit
1 = AN7 is using Signed Data mode
0 = AN7 is using Unsigned Data mode
bit 13 DIFF6: AN6 Mode bit
1 = AN6 is using Differential mode
0 = AN6 is using Single-ended mode
bit 12 SIGN6: AN6 Signed Data Mode bit
1 = AN6 is using Signed Data mode
0 = AN6 is using Unsigned Data mode
bit 11 DIFF5: AN5 Mode bit
1 = AN5 is using Differential mode
0 = AN5 is using Single-ended mode
bit 10 SIGN5: AN5 Signed Data Mode bit
1 = AN5 is using Signed Data mode
0 = AN5 is using Unsigned Data mode
bit 9 DIFF4: AN4 Mode bit
1 = AN4 is using Differential mode
0 = AN4 is using Single-ended mode
bit 8 SIGN4: AN4 Signed Data Mode bit
1 = AN4 is using Signed Data mode
0 = AN4 is using Unsigned Data mode
bit 7 DIFF3: AN3 Mode bit
1 = AN3 is using Differential mode
0 = AN3 is using Single-ended mode
bit 6 SIGN3: AN3 Signed Data Mode bit
1 = AN3 is using Signed Data mode
0 = AN3 is using Unsigned Data mode
bit 5 DIFF2: AN2 Mode bit
1 = AN2 is using Differential mode
0 = AN2 is using Single-ended mode
Register 22-5: ADCIMCON1: ADC Input Mode Control Register 1 (Continued)
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-21
Section 22. 12-bit High-Speed SAR ADC
bit 4 SIGN2: AN2 Signed Data Mode bit
1 = AN2 is using Signed Data mode
0 = AN2 is using Unsigned Data mode
bit 3 DIFF1: AN1 Mode bit
1 = AN1 is using Differential mode
0 = AN1 is using Single-ended mode
bit 2 SIGN1: AN1 Signed Data Mode bit
1 = AN1 is using Signed Data mode
0 = AN1 is using Unsigned Data mode
bit 1 DIFF0: AN0 Mode bit
1 = AN0 is using Differential mode
0 = AN0 is using Single-ended mode
bit 0 SIGN0: AN0 Signed Data Mode bit
1 = AN0 is using Signed Data mode
0 = AN0 is using Unsigned Data mode
Register 22-5: ADCIMCON1: ADC Input Mode Control Register 1 (Continued)
PIC32 Family Reference Manual
DS60001344E-page 22-22 © 2015-2019 Microchip Technology Inc.
Register 22-6: ADCIMCON2: ADC Input Mode Control Register 2
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF31 SIGN31 DIFF30 SIGN30 DIFF29 SIGN29 DIFF28 SIGN28
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF27 SIGN27 DIFF26 SIGN26 DIFF25 SIGN25 DIFF24 SIGN24
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF23 SIGN23 DIFF22 SIGN22 DIFF21 SIGN21 DIFF20 SIGN20
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF19 SIGN19 DIFF18 SIGN18 DIFF17 SIGN17 DIFF16 SIGN16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 DIFF31: AN31 Mode bit
1 = AN31 is using Differential mode
0 = AN31 is using Single-ended mode
bit 30 SIGN31: AN31 Signed Data Mode bit
1 = AN31 is using Signed Data mode
0 = AN31 is using Unsigned Data mode
bit 29 DIFF30: AN30 Mode bit
1 = AN30 is using Differential mode
0 = AN30 is using Single-ended mode
bit 28 SIGN30: AN30 Signed Data Mode bit
1 = AN30 is using Signed Data mode
0 = AN30 is using Unsigned Data mode
bit 27 DIFF29: AN29 Mode bit
1 = AN29 is using Differential mode
0 = AN29 is using Single-ended mode
bit 26 SIGN29: AN29 Signed Data Mode bit
1 = AN29 is using Signed Data mode
0 = AN29 is using Unsigned Data mode
bit 25 DIFF28: AN28 Mode bit
1 = AN28 is using Differential mode
0 = AN28 is using Single-ended mode
bit 24 SIGN28: AN28 Signed Data Mode bit
1 = AN28 is using Signed Data mode
0 = AN28 is using Unsigned Data mode
bit 23 DIFF27: AN27 Mode bit
1 = AN27 is using Differential mode
0 = AN27 is using Single-ended mode
bit 22 SIGN27: AN27 Signed Data Mode bit
1 = AN27 is using Signed Data mode
0 = AN27 is using Unsigned Data mode
bit 21 DIFF26: AN26 Mode bit
1 = AN26 is using Differential mode
0 = AN26 is using Single-ended mode
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-23
Section 22. 12-bit High-Speed SAR ADC
bit 20 SIGN26: AN26 Signed Data Mode bit
1 = AN26 is using Signed Data mode
0 = AN26 is using Unsigned Data mode
bit 19 DIFF25: AN25 Mode bit
1 = AN25 is using Differential mode
0 = AN25 is using Single-ended mode
bit 18 SIGN25: AN25 Signed Data Mode bit
1 = AN25 is using Signed Data mode
0 = AN25 is using Unsigned Data mode
bit 17 DIFF24: AN24 Mode bit
1 = AN24 is using Differential mode
0 = AN24 is using Single-ended mode
bit 16 SIGN24: AN24 Signed Data Mode bit
1 = AN24 is using Signed Data mode
0 = AN24 is using Unsigned Data mode
bit 15 DIFF23: AN23 Mode bit
1 = AN23 is using Differential mode
0 = AN23 is using Single-ended mode
bit 14 SIGN23: AN23 Signed Data Mode bit
1 = AN23 is using Signed Data mode
0 = AN23 is using Unsigned Data mode
bit 13 DIFF22: AN22 Mode bit
1 = AN22 is using Differential mode
0 = AN22 is using Single-ended mode
bit 12 SIGN22: AN22 Signed Data Mode bit
1 = AN22 is using Signed Data mode
0 = AN22 is using Unsigned Data mode
bit 11 DIFF21: AN21 Mode bit
1 = AN21 is using Differential mode
0 = AN21 is using Single-ended mode
bit 10 SIGN21: AN21 Signed Data Mode bit
1 = AN21 is using Signed Data mode
0 = AN21 is using Unsigned Data mode
bit 9 DIFF20: AN20 Mode bit
1 = AN20 is using Differential mode
0 = AN20 is using Single-ended mode
bit 8 SIGN20: AN20 Signed Data Mode bit
1 = AN20 is using Signed Data mode
0 = AN20 is using Unsigned Data mode
bit 7 DIFF19: AN19 Mode bit
1 = AN19 is using Differential mode
0 = AN19 is using Single-ended mode
bit 6 SIGN19: AN19 Signed Data Mode bit
1 = AN19 is using Signed Data mode
0 = AN19 is using Unsigned Data mode
bit 5 DIFF18: AN18 Mode bit
1 = AN18 is using Differential mode
0 = AN18 is using Single-ended mode
Register 22-6: ADCIMCON2: ADC Input Mode Control Register 2 (Continued)
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-25
Section 22. 12-bit High-Speed SAR ADC
Register 22-7: ADCIMCON3: ADC Input Mode Control Register 3
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF47 SIGN47 DIFF46 SIGN46 DIFF45 SIGN45 DIFF44 SIGN44
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF43 SIGN43 DIFF42 SIGN42 DIFF41 SIGN41 DIFF40 SIGN40
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF39 SIGN39 DIFF38 SIGN38 DIFF37 SIGN37 DIFF36 SIGN36
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF35 SIGN35 DIFF34 SIGN34 DIFF33 SIGN33 DIFF32 SIGN32
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 DIFF47: AN47 Mode bit
1 = AN47 is using Differential mode
0 = AN47 is using Single-ended mode
bit 30 SIGN47: AN47 Signed Data Mode bit
1 = AN47 is using Signed Data mode
0 = AN47 is using Unsigned Data mode
bit 29 DIFF46: AN46 Mode bit
1 = AN46 is using Differential mode
0 = AN46 is using Single-ended mode
bit 28 SIGN46: AN46 Signed Data Mode bit
1 = AN46 is using Signed Data mode
0 = AN46 is using Unsigned Data mode
bit 27 DIFF45: AN45 Mode bit
1 = AN45 is using Differential mode
0 = AN45 is using Single-ended mode
bit 26 SIGN45: AN45 Signed Data Mode bit
1 = AN45 is using Signed Data mode
0 = AN45 is using Unsigned Data mode
bit 25 DIFF44: AN44 Mode bit
1 = AN44 is using Differential mode
0 = AN44 is using Single-ended mode
bit 24 SIGN44: AN44 Signed Data Mode bit
1 = AN44 is using Signed Data mode
0 = AN44 is using Unsigned Data mode
bit 23 DIFF43: AN43 Mode bit
1 = AN43 is using Differential mode
0 = AN43 is using Single-ended mode
bit 22 SIGN43: AN43 Signed Data Mode bit
1 = AN43 is using Signed Data mode
0 = AN43 is using Unsigned Data mode
bit 21 DIFF42: AN42 Mode bit
1 = AN42 is using Differential mode
0 = AN42 is using Single-ended mode
PIC32 Family Reference Manual
DS60001344E-page 22-26 © 2015-2019 Microchip Technology Inc.
bit 20 SIGN42: AN42 Signed Data Mode bit
1 = AN42 is using Signed Data mode
0 = AN42 is using Unsigned Data mode
bit 19 DIFF41: AN41 Mode bit
1 = AN41 is using Differential mode
0 = AN41 is using Single-ended mode
bit 18 SIGN41: AN41 Signed Data Mode bit
1 = AN41 is using Signed Data mode
0 = AN41 is using Unsigned Data mode
bit 17 DIFF40: AN40 Mode bit
1 = AN40 is using Differential mode
0 = AN40 is using Single-ended mode
bit 16 SIGN40: AN40 Signed Data Mode bit
1 = AN40 is using Signed Data mode
0 = AN40 is using Unsigned Data mode
bit 15 DIFF39: AN39 Mode bit
1 = AN39 is using Differential mode
0 = AN39 is using Single-ended mode
bit 14 SIGN39: AN39 Signed Data Mode bit
1 = AN39 is using Signed Data mode
0 = AN39 is using Unsigned Data mode
bit 13 DIFF38: AN38 Mode bit
1 = AN38 is using Differential mode
0 = AN38 is using Single-ended mode
bit 12 SIGN38: AN38 Signed Data Mode bit
1 = AN38 is using Signed Data mode
0 = AN38 is using Unsigned Data mode
bit 11 DIFF37: AN37 Mode bit
1 = AN37 is using Differential mode
0 = AN37 is using Single-ended mode
bit 10 SIGN37: AN37 Signed Data Mode bit
1 = AN37 is using Signed Data mode
0 = AN37 is using Unsigned Data mode
bit 9 DIFF36: AN36 Mode bit
1 = AN36 is using Differential mode
0 = AN36 is using Single-ended mode
bit 8 SIGN36: AN36 Signed Data Mode bit
1 = AN36 is using Signed Data mode
0 = AN36 is using Unsigned Data mode
bit 7 DIFF35: AN35 Mode bit
1 = AN35 is using Differential mode
0 = AN35 is using Single-ended mode
bit 6 SIGN35: AN35 Signed Data Mode bit
1 = AN35 is using Signed Data mode
0 = AN35 is using Unsigned Data mode
bit 5 DIFF34: AN34 Mode bit
1 = AN34 is using Differential mode
0 = AN34 is using Single-ended mode
Register 22-7: ADCIMCON3: ADC Input Mode Control Register 3 (Continued)
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-27
Section 22. 12-bit High-Speed SAR ADC
bit 4 SIGN34: AN34 Signed Data Mode bit
1 = AN34 is using Signed Data mode
0 = AN34 is using Unsigned Data mode
bit 3 DIFF33: AN33 Mode bit
1 = AN33 is using Differential mode
0 = AN33 is using Single-ended mode
bit 2 SIGN33: AN33 Signed Data Mode bit
1 = AN33 is using Signed Data mode
0 = AN33 is using Unsigned Data mode
bit 1 DIFF32: AN32 Mode bit
1 = AN32 is using Differential mode
0 = AN32 is using Single-ended mode
bit 0 SIGN32: AN32 Signed Data Mode bit
1 = AN32 is using Signed Data mode
0 = AN32 is using Unsigned Data mode
Register 22-7: ADCIMCON3: ADC Input Mode Control Register 3 (Continued)
PIC32 Family Reference Manual
DS60001344E-page 22-28 © 2015-2019 Microchip Technology Inc.
Register 22-8: ADCIMCON4: ADC Input Mode Control Register 4
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF63 SIGN63 DIFF62 SIGN62 DIFF61 SIGN61 DIFF60 SIGN60
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF59 SIGN59 DIFF58 SIGN58 DIFF57 SIGN57 DIFF56 SIGN56
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF55 SIGN55 DIFF54 SIGN54 DIFF53 SIGN53 DIFF52 SIGN52
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIFF51 SIGN51 DIFF50 SIGN50 DIFF49 SIGN49 DIFF48 SIGN48
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 DIFF63: AN63 Mode bit
1 = AN63 is using Differential mode
0 = AN63 is using Single-ended mode
bit 30 SIGN63: AN63 Signed Data Mode bit
1 = AN63 is using Signed Data mode
0 = AN63 is using Unsigned Data mode
bit 29 DIFF62: AN62 Mode bit
1 = AN62 is using Differential mode
0 = AN62 is using Single-ended mode
bit 28 SIGN62: AN62 Signed Data Mode bit
1 = AN62 is using Signed Data mode
0 = AN62 is using Unsigned Data mode
bit 27 DIFF61: AN61 Mode bit
1 = AN61 is using Differential mode
0 = AN61 is using Single-ended mode
bit 26 SIGN61: AN61 Signed Data Mode bit
1 = AN61 is using Signed Data mode
0 = AN61 is using Unsigned Data mode
bit 25 DIFF60: AN60 Mode bit
1 = AN60 is using Differential mode
0 = AN60 is using Single-ended mode
bit 24 SIGN60: AN60 Signed Data Mode bit
1 = AN60 is using Signed Data mode
0 = AN60 is using Unsigned Data mode
bit 23 DIFF59: AN59 Mode bit
1 = AN59 is using Differential mode
0 = AN59 is using Single-ended mode
bit 22 SIGN59: AN59 Signed Data Mode bit
1 = AN59 is using Signed Data mode
0 = AN59 is using Unsigned Data mode
bit 21 DIFF58: AN58 Mode bit
1 = AN58 is using Differential mode
0 = AN58 is using Single-ended mode
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-29
Section 22. 12-bit High-Speed SAR ADC
bit 20 SIGN58: AN58 Signed Data Mode bit
1 = AN58 is using Signed Data mode
0 = AN58 is using Unsigned Data mode
bit 19 DIFF57: AN57 Mode bit
1 = AN57 is using Differential mode
0 = AN57 is using Single-ended mode
bit 18 SIGN57: AN57 Signed Data Mode bit
1 = AN57 is using Signed Data mode
0 = AN57 is using Unsigned Data mode
bit 17 DIFF56: AN56 Mode bit
1 = AN56 is using Differential mode
0 = AN56 is using Single-ended mode
bit 16 SIGN56: AN56 Signed Data Mode bit
1 = AN56 is using Signed Data mode
0 = AN56 is using Unsigned Data mode
bit 15 DIFF55: AN55 Mode bit
1 = AN55 is using Differential mode
0 = AN55 is using Single-ended mode
bit 14 SIGN55: AN55 Signed Data Mode bit
1 = AN55 is using Signed Data mode
0 = AN55 is using Unsigned Data mode
bit 13 DIFF54: AN54 Mode bit
1 = AN54 is using Differential mode
0 = AN54 is using Single-ended mode
bit 12 SIGN54: AN54 Signed Data Mode bit
1 = AN54 is using Signed Data mode
0 = AN54 is using Unsigned Data mode
bit 11 DIFF53: AN53 Mode bit
1 = AN53 is using Differential mode
0 = AN53 is using Single-ended mode
bit 10 SIGN53: AN53 Signed Data Mode bit
1 = AN53 is using Signed Data mode
0 = AN53 is using Unsigned Data mode
bit 9 DIFF52: AN52 Mode bit
1 = AN52 is using Differential mode
0 = AN52 is using Single-ended mode
bit 8 SIGN52: AN52 Signed Data Mode bit
1 = AN52 is using Signed Data mode
0 = AN52 is using Unsigned Data mode
bit 7 DIFF51: AN51 Mode bit
1 = AN51 is using Differential mode
0 = AN51 is using Single-ended mode
bit 6 SIGN51: AN51 Signed Data Mode bit
1 = AN51 is using Signed Data mode
0 = AN51 is using Unsigned Data mode
bit 5 DIFF50: AN50 Mode bit
1 = AN50 is using Differential mode
0 = AN50 is using Single-ended mode
Register 22-8: ADCIMCON4: ADC Input Mode Control Register 4 (Continued)
PIC32 Family Reference Manual
DS60001344E-page 22-30 © 2015-2019 Microchip Technology Inc.
bit 4 SIGN50: AN50 Signed Data Mode bit
1 = AN50 is using Signed Data mode
0 = AN50 is using Unsigned Data mode
bit 3 DIFF49: AN49 Mode bit
1 = AN49 is using Differential mode
0 = AN49 is using Single-ended mode
bit 2 SIGN49: AN49 Signed Data Mode bit
1 = AN49 is using Signed Data mode
0 = AN49 is using Unsigned Data mode
bit 1 DIFF48: AN48 Mode bit
1 = AN48 is using Differential mode
0 = AN48 is using Single-ended mode
bit 0 SIGN48: AN48 Signed Data Mode bit
1 = AN48 is using Signed Data mode
0 = AN48 is using Unsigned Data mode
Register 22-8: ADCIMCON4: ADC Input Mode Control Register 4 (Continued)
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-31
Section 22. 12-bit High-Speed SAR ADC
Register 22-9: ADCGIRQEN1: ADC Global Interrupt Enable Register 1
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AGIEN31 AGIEN30 AGIEN29 AGIEN28 AGIEN27 AGIEN26 AGIEN25 AGIEN24
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AGIEN23 AGIEN22 AGIEN21 AGIEN20 AGIEN19 AGIEN18 AGIEN17 AGIEN16
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AGIEN15 AGIEN14 AGIEN13 AGIEN12 AGIEN11 AGIEN10 AGIEN9 AGIEN8
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AGIEN7 AGIEN6 AGIEN5 AGIEN4 AGIEN3 AGIEN2 AGIEN1 AGIEN0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 AGIEN31:AGIEN0: ADC Interrupt Enable bits
1 = Interrupts are enabled for the selected analog input. The interrupt is generated after the converted
data is ready (indicated by the ARDYx bit (‘x’ = 31-0) of the ADCDSTAT1 register)
0 = Interrupts are disabled
Register 22-10: ADCGIRQEN2: ADC Global Interrupt Enable Register 2
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AGIEN63 AGIEN62 AGIEN61 AGIEN60 AGIEN59 AGIEN58 AGIEN57 AGIEN56
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AGIEN55 AGIEN54 AGIEN53 AGIEN52 AGIEN51 AGIEN50 AGIEN49 AGIEN48
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AGIEN47 AGIEN46 AGIEN45 AGIEN44 AGIEN43 AGIEN42 AGIEN41 AGIEN40
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AGIEN39 AGIEN38 AGIEN37 AGIEN36 AGIEN35 AGIEN34 AGIEN33 AGIEN32
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 AGIEN63:AGIEN32 ADC Interrupt Enable bits
1 = Interrupts are enabled for the selected analog input. The interrupt is generated after the converted
data is ready (indicated by the ARDYx bit (‘x’ = 63-32) of the ADCDSTAT2 register)
0 = Interrupts are disabled
PIC32 Family Reference Manual
DS60001344E-page 22-32 © 2015-2019 Microchip Technology Inc.
Register 22-11: ADCCSS1: ADC Common Scan Select Register 1
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CSS31:CSS0: Analog Common Scan Select bits
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1: In addition to setting the appropriate bits in this register, Class 1 and Class 2 analog inputs must select the
STRIG input as the trigger source if they are to be scanned through the CSS bits. Refer to the bit x
descriptions in the ADCTRGx register (Register 22-18) for selecting the STRIG option.
2: If a Class 1 or Class 2 input is included in the scan by setting the CSSx bit to ‘1’ and by setting the
TRGSRCx<4:0> bits to STRIG mode (‘0b11), the user application must ensure that no other triggers are
generated for that input using the RQCNVRT bit in the ADCCON3 register or the hardware input or any
digital filter. Otherwise, the scan behavior is unpredictable.
Register 22-12: ADCCSS2: ADC Common Scan Select Register 2
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS63 CSS62 CSS61 CSS60 CSS59 CSS58 CSS57 CSS56
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS55 CSS54 CSS53 CSS52 CSS51 CSS50 CSS49 CSS48
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS47 CSS46 CSS45 CSS44 CSS43 CSS42 CSS41 CSS40
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS39 CSS38 CSS37 CSS36 CSS35 CSS34 CSS33 CSS32
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CSS63:CSS32: Analog Common Scan Select bits
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note: Analog inputs 63 to 32 are always Class 3, as there are only 32 triggers available.
PIC32 Family Reference Manual
DS60001344E-page 22-34 © 2015-2019 Microchip Technology Inc.
Register 22-15: ADCCMPENx: ADC Digital Comparator ‘x’ Enable Register (‘x’ = 1 through 6)
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CMPE31 CMPE30 CMPE29 CMPE28 CMPE27 CMPE26 CMPE25 CMPE24
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CMPE23 CMPE22 CMPE21 CMPE20 CMPE19 CMPE18 CMPE17 CMPE16
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CMPE15 CMPE14 CMPE13 CMPE12 CMPE11 CMPE10 CMPE9 CMPE8
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CMPE7 CMPE6 CMPE5 CMPE4 CMPE3 CMPE2 CMPE1 CMPE0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CMPE31:CMPE0: ADC Digital Comparator ‘x’ Enable bits
These bits enable conversion results corresponding to the Analog Input to be processed by the Digital
Comparator. CMPE0 enables AN0, CMPE1 enables AN1, and so on.
Note 1: CMPEx = ANx, where ‘x’ = 0-31 (Digital Comparator inputs are limited to AN0 through AN31).
2: Changing the bits in this register while the Digital Comparator is enabled (ENDCMP = 1) can result in
unpredictable behavior.
Register 22-16: ADCCMPx: ADC Digital Comparator ‘x’ Limit Value Register (‘x’ = 1 through 6)
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCMPHI<15:8>
(1,2,3)
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCMPHI<7:0>
(1,2,3)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCMPLO<15:8>
(1,2,3)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCMPLO<7:0>
(1,2,3)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 DCMPHI<15:0>: Digital Comparator ‘x’ High Limit Value bits
(1,2,3)
These bits store the high limit value, which is used by digital comparator for comparisons with ADC
converted data.
bit 15-0 DCMPLO<15:0>: Digital Comparator ‘x’ Low Limit Value bits
(1,2,3)
These bits store the low limit value, which is used by digital comparator for comparisons with ADC
converted data.
Note 1: Changing theses bits while the Digital Comparator is enabled (E ) can result in unpredictable NDCMP = 1
behavior.
2: The format of the limit values should match the format of the ADC converted value in terms of sign and
fractional settings.
3: For Digital Comparator 1 used in CVD mode, the DCMPHI<15:0> and DCMPLO<15:0> bits must always
be specified in signed format, as the CVD output data is differential and is always signed.
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-35
Section 22. 12-bit High-Speed SAR ADC
Register 22-17: ADCFLTRx: ADC Digital Filter ‘x’ Register (‘x’ =
1
through
6)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC
AFEN DATA16EN DFMODE OVRSAM<2:0> AFGIEN AFRDY
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — CHNLID<4:0>
15:8
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
FLTRDATA<15:8>
7:0
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
FLTRDATA<7:0>
Legend: HS = Hardware Set HC = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 AFEN: Digital Filter ‘x’ Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled and the AFRDY status bit is cleared
bit 30 DATA16EN: Filter Significant Data Length bit
1 = All 16 bits of the filter output data are significant
0 = Only the first 12 bits are significant, followed by four zeros
Note: This bit is significant only if DFMODE = 1 (Averaging Mode) and FRACT (ADCCON1<23>) = 1
(Fractional Output Mode).
bit 29 DFMODE: ADC Filter Mode bit
1 = Filter ‘x’ works in Averaging mode
0 = Filter ‘x’ works in Oversampling Filter mode (default)
When the ADC filter is enabled and DFMODE = 0:
Once an ADC edge conversion trigger event occurs, it is held active until the filter OVRSAM sample count
has expired.
The Minimum Trigger Period = (OVRSAM<2:0> bits in ADCFLTRx) (SAMC<7:0> bits in ADCxTIME T
AD
+
((SELRES<1:0> bits in ADCxTIME + 1) T
AD
).
Example:
• OVRSAM<2:0> bits in ADCFLTRx = 8x Samples
• SAMC<7:0> bits in ADCxTIME = 3 T
AD
• SELRES<1:0> bits in ADCxTIME = 12 bits
User Min Trig period ≥ (8 * (3 T
AD
+ 13 T
AD
)) = 128 T
AD
When the ADC filter is enabled and DFMODE = 1:
All ADC conversions are initiated solely by trigger events. After OVRSAM normal edge trigger events and
subsequent conversions, the ADC filter result will contain the average value of OVRSAM number of
conversions.
Refer to Figure 22-18: “ADC Filter Comparisons Example” for more information.
PIC32 Family Reference Manual
DS60001344E-page 22-36 © 2015-2019 Microchip Technology Inc.
bit 28-26 OVRSAM<2:0>: Oversampling Filter Ratio bits
If DFMODE is ‘0’:
111 = 128 samples (shift sum 3 bits to right, output data is in 15.1 format)
110 = 32 samples (shift sum 2 bits to right, output data is in 14.1 format)
101 = 8 samples (shift sum 1 bit to right, output data is in 13.1 format)
100 = 2 samples (shift sum 0 bits to right, output data is in 12.1 format)
011 = 256 samples (shift sum 4 bits to right, output data is 16 bits)
010 = 64 samples (shift sum 3 bits to right, output data is 15 bits)
001 = 16 samples (shift sum 2 bits to right, output data is 14 bits)
000 = 4 samples (shift sum 1 bit to right, output data is 13 bits)
If DFMODE is ‘1’:
111 = 256 samples (256 samples to be averaged)
110 = 128 samples (128 samples to be averaged)
101 = 64 samples (64 samples to be averaged)
100 = 32 samples (32 samples to be averaged)
011 = 16 samples (16 samples to be averaged)
010 = 8 samples (8 samples to be averaged)
001 = 4 samples (4 samples to be averaged)
000 = 2 samples (2 samples to be averaged)
bit 25 AFGIEN: Digital Filter ‘x’ Interrupt Enable bit
1 = Digital filter interrupt is enabled and is generated by the AFRDY status bit
0 = Digital filter is disabled
bit 24 AFRDY: Digital Filter ‘x’ Data Ready Status bit
1 = Data is ready in the FLTRDATA<15:0> bits
0 = Data is not ready
Note: This bit is cleared by reading the FLTRDATA<15:0> bits or by disabling the Digital Filter module
(by setting AFEN to ‘0’).
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 CHNLID<4:0>: Digital Filter Analog Input Selection bits
These bits specify the analog input to be used as the oversampling filter data source.
11111 = AN31
•
•
•
00010 = AN2
00001 = AN1
00000 = AN0
Note: Only the first 32 analog inputs (Class 1 and Class 2) can use a digital filter.
bit 15-0 FLTRDATA<15:0>: Digital Filter ‘ ’ Data Output Value bitsx
The filter output data is as per the fractional format set in the FRACT bit (ADCCON1<23>). The FRACT bit
should not be changed while the filter is enabled. Changing the state of the FRACT bit after the operation
of the filter has ended will not update the value of the FLTRDATA<15:0> bits to reflect the new format.
Register 22-17: ADCFLTRx: ADC Digital Filter ‘x’ Register (‘x’ =
1
through
6)
(Continued)
PIC32 Family Reference Manual
DS60001344E-page 22-38 © 2015-2019 Microchip Technology Inc.
Register 22-19: ADCTRG2: ADC Trigger Source 2 Register
Bit
Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC7<4:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC6<4:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC5<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC4<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC7<4:0>: Trigger Source for Conversion of Analog Input AN7 Select bits
11111 00100 - = Refer to the “ADC” chapter in the specific device data sheet for trigger source selections
00011 = Scan Trigger (STRIG)
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge Trigger (GSWTRG)
00000 = No Trigger
For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits
(ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSSx bits to be set in the
ADCCSSx registers.
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC6<4:0>: Trigger Source for Conversion of Analog Input AN6 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC5<4:0>: Trigger Source for Conversion of Analog Input AN5 Select bits
See bits 28-24 for bit value definitions.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TRGSRC4<4:0>: Trigger Source for Conversion of Analog Input AN4 Select bits
See bits 28-24 for bit value definitions.
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-39
Section 22. 12-bit High-Speed SAR ADC
Register 22-20: ADCTRG3: ADC Trigger Source 3 Register
Bit
Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC11<4:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC10<4:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC9<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC8<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC11<4:0>: Trigger Source for Conversion of Analog Input AN11 Select bits
11111 00100 - = Refer to the “ADC” chapter in the specific device data sheet for trigger source selections
00011 = Scan Trigger (STRIG)
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge Trigger (GSWTRG)
00000 = No Trigger
For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits
(ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSSx bits to be set in the
ADCCSSx registers.
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC10<4:0>: Trigger Source for Conversion of Analog Input AN10 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC9<4:0>: Trigger Source for Conversion of Analog Input AN9 Select bits
See bits 28-24 for bit value definitions.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TRGSRC8<4:0>: Trigger Source for Conversion of Analog Input AN8 Select bits
See bits 28-24 for bit value definitions.
PIC32 Family Reference Manual
DS60001344E-page 22-40 © 2015-2019 Microchip Technology Inc.
Register 22-21: ADCTRG4: ADC Trigger Source 4 Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC15<4:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC14<4:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC13<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC12<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC15<4:0>: Trigger Source for Conversion of Analog Input AN15 Select bits
11111 00100 - = Refer to the “ADC” chapter in the specific device data sheet for trigger source selections
00011 = Scan Trigger (STRIG)
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge Trigger (GSWTRG)
00000 = No Trigger
For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits
(ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSSx bits to be set in the
ADCCSSx registers.
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC14<4:0>: Trigger Source for Conversion of Analog Input AN14 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC13<4:0>: Trigger Source for Conversion of Analog Input AN13 Select bits
See bits 28-24 for bit value definitions.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TRGSRC12<4:0>: Trigger Source for Conversion of Analog Input AN12 Select bits
See bits 28-24 for bit value definitions.
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-41
Section 22. 12-bit High-Speed SAR ADC
Register 22-22: ADCTRG5: ADC Trigger Source 5 Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC19<4:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC18<4:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC17<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC16<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC19<4:0>: Trigger Source for Conversion of Analog Input AN19 Select bits
11111 00100 - = Refer to the “ADC” chapter in the specific device data sheet for trigger source selections
00011 = Scan Trigger (STRIG)
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge Trigger (GSWTRG)
00000 = No Trigger
For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits
(ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSSx bits to be set in the
ADCCSSx registers.
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC18<4:0>: Trigger Source for Conversion of Analog Input AN18 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC17<4:0>: Trigger Source for Conversion of Analog Input AN17 Select bits
See bits 28-24 for bit value definitions.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TRGSRC16<4:0>: Trigger Source for Conversion of Analog Input AN16 Select bits
See bits 28-24 for bit value definitions.
PIC32 Family Reference Manual
DS60001344E-page 22-42 © 2015-2019 Microchip Technology Inc.
Register 22-23: ADCTRG6: ADC Trigger Source 6 Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC23<4:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC22<4:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC21<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC20<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC23<4:0>: Trigger Source for Conversion of Analog Input AN23 Select bits
11111-00100 = Refer to the “ADC” chapter in the specific device data sheet for information
00011 = Scan Trigger (STRIG)
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge Trigger (GSWTRG)
00000 = No Trigger
For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits
(ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSSx bits to be set in the
ADCCSSx registers.
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC22<4:0>: Trigger Source for Conversion of Analog Input AN22 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC21<4:0>: Trigger Source for Conversion of Analog Input AN21 Select bits
See bits 28-24 for bit value definitions.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TRGSRC20<4:0>: Trigger Source for Conversion of Analog Input AN20 Select bits
See bits 28-24 for bit value definitions.
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-43
Section 22. 12-bit High-Speed SAR ADC
Register 22-24: ADCTRG7: ADC Trigger Source 7 Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC27<4:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC26<4:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC25<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC24<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC27<4:0>: Trigger Source for Conversion of Analog Input AN27 Select bits
11111-00100 = Refer to the “ADC” chapter in the specific device data sheet for information
00011 = Scan Trigger (STRIG)
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge Trigger (GSWTRG)
00000 = No Trigger
For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits
(ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSSx bits to be set in the
ADCCSSx registers.
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC26<4:0>: Trigger Source for Conversion of Analog Input AN26 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC25<4:0>: Trigger Source for Conversion of Analog Input AN25 Select bits
See bits 28-24 for bit value definitions.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TRGSRC24<4:0>: Trigger Source for Conversion of Analog Input AN24 Select bits
See bits 28-24 for bit value definitions.
PIC32 Family Reference Manual
DS60001344E-page 22-44 © 2015-2019 Microchip Technology Inc.
Register 22-25: ADCTRG8: ADC Trigger Source 8 Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC31<4:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC30<4:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC29<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC28<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC31<4:0>: Trigger Source for Conversion of Analog Input AN31 Select bits
11111-00100 = Refer to the “ADC” chapter in the specific device data sheet for information
00011 = Scan Trigger (STRIG)
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge Trigger (GSWTRG)
00000 = No Trigger
For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits
(ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSSx bits to be set in the
ADCCSSx registers.
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC30<4:0>: Trigger Source for Conversion of Analog Input AN30 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC29<4:0>: Trigger Source for Conversion of Analog Input AN29 Select bits
See bits 28-24 for bit value definitions.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TRGSRC28<4:0>: Trigger Source for Conversion of Analog Input AN28 Select bits
See bits 28-24 for bit value definitions.
© 2015-2019 Microchip Technology Inc. DS60001344E-page 22-45
Section 22. 12-bit High-Speed SAR ADC
Register 22-26: ADCCMPCON1: ADC Digital Comparator 1 Control Register
Bit Range Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
CVDDATA<15:8>
23:16
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
CVDDATA<7:0>
15:8
U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
— — AINID<5:0>
7:0
R/W-0 R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ENDCMP DCMPGIEN DCMPED IEBTWN IEHIHI IEHILO IELOHI IELOLO
Legend: HS = Hardware Set HC = Hardware Cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 CVDDATA<15:0>: CVD Data Status bits
In CVD mode, these bits obtain the CVD differential output data (subtraction of CVD positive and negative
measurement), whenever a Digital Comparator event is generated. The value in these bits is compliant
with the FRACT bit (ADCCON1<23>) and is always signed.
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 AINID<5:0>: Digital Comparator 1 Analog Input Identification (ID) bits
When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being
monitored by Digital Comparator 1.
Note: In normal ADC mode, only analog inputs <31:0> can be processed by the Digital Comparator 1.
The Digital Comparator 1 also supports the CVD mode, in which Class 2 and Class 3 analog
inputs may be stored in the AINID<5:0> bits.
111111 = AN63 is being monitored
111110 = AN62 is being monitored
•
•
•
000001 = AN1 is being monitored
000000 = AN0 is being monitored
bit 7 ENDCMP: Digital Comparator 1 Enable bit
1 = Digital Comparator 1 is enabled
0 = Digital Comparator 1 is not enabled, and the DCMPED status bit (ADCCMPCON1<5>) is cleared
bit 6 DCMPGIEN: Digital Comparator 1 Interrupt Enable bit
1 = A Digital Comparator 1 interrupt is generated when the DCMPED status bit (ADCCMPCON1<5>) is set
0 = A Digital Comparator 1 interrupt is disabled
bit 5 DCMPED: Digital Comparator 1 “Output True” Event Status bit
The logical conditions under which the digital comparator gets “True” are defined by the IEBTWN, IEHIHI,
IEHILO, IELOHI, and IELOLO bits.
Note: This bit is cleared by reading the AINID<5:0> bits or by disabling the Digital Comparator module
(by setting ENDCMP to ‘0’).
1 = Digital Comparator 1 output true event has occurred (output of Comparator is ‘1’)
0 = Digital Comparator 1 output is false (output of comparator is ‘0’)
bit 4 IEBTWN: Between Low/High Digital Comparator 1 Event bit
1 = Generate a digital comparator event when DCMPLO<15:0> DATA<31:0>
<
DCMPHI<15:0>
0 = Do not generate a digital comparator event
bit 3 IEHIHI: High/High Digital Comparator 1 Event bit
1 = Generate a Digital Comparator 1 Event when DCMPHI<15:0> DATA<31:0>
0 = Do not generate an event
bit 2 IEHILO: High/Low Digital Comparator 1 Event bit
1 = Generate a Digital Comparator 1 Event when DATA<31:0>
<
DCMPHI<15:0>
0 = Do not generate an event
Produkt Specifikationer
| Mærke: | Microchip |
| Kategori: | Ikke kategoriseret |
| Model: | PIC32MZ1024EFE064 |
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