Microchip PIC32MZ2048ECG144 Manual
Microchip
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PIC32MZ2048ECG144
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© 2009-2017 Microchip Technology Inc. DS60001155D-page 35-1
Section 35. Ethernet Controller
This section of the manual contains the following major topics:
35.1 Introduction .............................................................................................................. 35-2
35.2 Ethernet Controller Overview .................................................................................. 35-3
35.3 Status and Control Registers................................................................................... 35-4
35.4 Operation...............................................................................................................35-43
35.5 Ethernet Interrupts................................................................................................. 35-82
35.6 Operation in Power-Saving and Debug Modes ..................................................... 35-87
35.7 Effects of Various Resets....................................................................................... 35-90
35.8 I/O Pin Control ....................................................................................................... 35-91
35.9 Related Application Notes ..................................................................................... 35-92
35.10 Revision History..................................................................................................... 35-93
PIC32 Family Reference Manual
DS60001155D-page 35-2 © 2009-2017 Microchip Technology Inc.
35.1 INTRODUCTION
The Ethernet Controller is a bus master module that interfaces with an off-chip PHY to implement
a complete Ethernet node in an embedded system.
The following are key features of the Ethernet Controller module:
• Supports 10/100 Mbps data transfer rates (see the Caution note in 35.4 “Operation”)
• Supports the full-duplex and half-duplex operation
• Supports the Reduced Media Independent Interface (RMII) and Media Independent
Interface (MII) PHY interface
• Supports the MII Management (MIIM) PHY Management interface
• Supports manual and automatic Flow Control
• Supports Auto-MDIX and enabled PHYs
• RAM descriptor based Direct Memory Access (DMA) operation for receive and transmit
path
• Fully configurable interrupts
• Configurable receive packet filtering
- Cyclic Redundancy Check (CRC)
- 64-byte pattern match
- Broadcast, multicast, and unicast packets
- Magic Packet™
- 64-bit Hash table
- Runt packet
• Supports Packet Payload Checksum calculation
• Supports various hardware statistics counters
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “Ethernet Controller” chapter in
the current device data sheet to check whether this document supports the device
you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
Note: To avoid cache coherency problems on devices with L1 cache, it is recommended
to access the Ethernet buffers from the KSEG1 segment.
Produkt Specifikationer
| Mærke: | Microchip |
| Kategori: | Ikke kategoriseret |
| Model: | PIC32MZ2048ECG144 |
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