
User Guide
© 2023 Microchip Technology Inc. and its subsidiaries
DS50003574B - 1
Introducon (Ask a Queson)
RTG4
™
FPGAs feature the fourth-generation FPGA fabric with radiation tolerance. Fabric is the programmable
logic section of the RTG4 FPGA, which you can use to congure with VHDL or Verilog. The RTG4 FPGA fabric
consists of the following resources:
• Logic elements: These are basic building blocks in the RTG4 FPGA.
• Embedded memory blocks: These include large SRAM (LSRAM), microSRAM (µSRAM), and microPROM
(µPROM).
• Math blocks: These have a built-in multiplier and adder.
The Libero
®
System-on-Chip (SoC) software (or third-party synthesis tools) automatically infers these logic
elements, embedded memories, and math blocks from the user’s Register Transfer Level (RTL) code. For more
information about the Libero SoC Classic and Enhanced Constraint design ow, see the Libero SoC Classic
Constraint Flow User Guide and Libero SoC for Enhanced Constraint Flow(ECF) User Guide.
The following gure is a top-level functional block diagram of the RTG4 FPGA family. The highlighted fabric block
is described in this document.
Figure 1. Funconal Block Diagram of RTG4 Family Device
FPGA Fabric Up to 150K Logic Elements
µPROM
16 SpaceWire Clock and Data
Recovery Circuits
Multi-Standard GPIO
(1.2 –V, LVTTL, LVCMOS, LVDS, HSTL/SSTL, PCI)
Math Blocks
(18x18)
PCI Express
x1, x2, x4
2 Per Device
XAUI
XGXS
Native SerDes
EPCS
Math Blocks
(18x18)
462
Micro SRAM
(64x18)
Micro SRAM
(64x18)
210
Large SRAM
(1024x18)
Large SRAM
(1024x18)
209
POR
Generator
JTAG
System
Controller
RT PLLs
24 Lanes Multi Protocol 3.125G SERDES
AXI/AHB
AXI/AHB, XGMII, Direct 20-bit Bus
667 Mbps DDR
Controller/PHY
AXI/AHB
667 Mbps DDR
Controller/PHY
Standard Cell/SEL Immune
Flash Based/SEL Immune
PMA PMA PMA PMA
RC OSC
The following
gure shows the fabric layout. The FPGA logic resources are displayed as Logic Clusters (LC). Each
LC consists of 12 Logic Elements (LEs). The embedded memory blocks and math blocks are arranged in rows.
RTG4 Fabric User Guide