Microchip USB3346 Manual

Microchip Ikke kategoriseret USB3346

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2010-2019 Microchip Technology Inc. DS00002971A-page 1
INTRODUCTION
The USB334x provides the physical layer interface (PHY) 2.0. Proper design tech-in systems using Hi-Speed USB
niques must be used in the printed circuit board (PCB) layout to maintain the signal integrity required for 480 Mbps oper-
ation. The USB334x is available in both 24-pin and 32-pin QFN packages; layout guidelines for general QFN packages
are provided in this application note.
Audience
This document is written for a reader that is familiar with hardware design and the USB 2.0 specification. The goal of
this application note is to provide guidance on sensitive areas of the PCB layout.
Overview
The following recommendations are for a four layer PCB layout with a Microchip part. Our recommendations are not the
only way to layout our 24-pin and 32-pin QFN packages. PCB design engineers will have his/her own preference, and
the implementation will be dependent on complexity and density of layout, PCB real estate, number and types of devices
in circuit and the environment that the final product will reside in. For example, the PCB described in this application
note has components on both sides of the board. A four layer board could be realized with components on one side only.
References
The following documents should be referenced when using this application note:
• Microchip USB334x Data Sheets
• Universal Serial Bus Specification Revision 2.0
AN 22.3
USB334x USB Transceiver Layout Guidelines
AN 22.3
DS00002971A-page 2 2010-2019 Microchip Technology Inc.
GENERAL DESIGN GUIDELINES
This section provides guidelines for the sensitive circuits associated with the system application of the USB334x.
ULPI Bus
The layout of the ULPI interface should be analyzed with the timing requirements of the USB Link controller to ensure
that the proper timing is met. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
For more information on ULPI timing and system design, refer to Application Note 19.17 - “ULPI Design Guide”.
Controlled Impedance for USB Traces
The USB 2.0 specification requires that the USB DP/DM traces maintain a nominal 90 Ohms differential impedance +/
- 15% (see USB specification Rev 2.0, paragraph 7.1.1.3 for more details). In this design example, the traces are 7 mil
(0.178mm) wide with line spacing of 7 mils (0.178mm). These numbers are derived for 5 mil (0.127mm) distance from
ground reference plane. For different dielectric thickness, copper weight or board stack-up, trace width and spacing will
need to be recalculated. A continuous ground plane is required directly beneath the DP/DM traces and extending at
least 5 times the spacing width to either side of DP/DM lines.
Maintain symmetry between DP/DM lines in regards to shape and length.
Single ended impedance is not as critical as the differential impedance. A range of 42 Ohms to 78 Ohms is acceptable
(equivalently, common mode impedance must be between 21 Ohms and 39 Ohms).
Figure 1 shows DP/DM traces with approximately equal trace length and symmetry. It is important to maintain a con-
ductor width and spacing that provides differential and common mode impedances compliant with the USB specification.
Use 45 degree turns to minimize impedance discontinuities.
FIGURE 1: EXAMPLE OF ROUTING DP/DM FROM QFN PKG TO TYPE B CONNECTOR

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Model: USB3346

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