Microchip USB3613 Manual


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2012-2019 Microchip Technology Inc. DS00001876C-page 1
1.0 INTRODUCTION
This application note provides information on general printed circuit board layout considerations for Microchip’s many
families of USB Hub Controller devices. This information is broadly applicable to any of Microchip’s USB 2.0 and USB
3.1 Gen 1 and Gen 2 device implementations.
1.1 Audience
This application note is written for readers that are familiar with PCB design, including signal integrity, differential sig-
naling, and thermal management implementation concepts.
1.2 Objective
The goal of this document is to provide implementation information that specifically applies to designing PCBs using
Microchip’s High Speed and faster families of USB Hub Controller devices. Careful implementation of these guidelines
enables successful designs.
1.3 Overview
Successful operation of Microchip’s USB Hub Controllers requires special consideration for printed circuit board (PCB)
layout. All Microchip USB Hub controllers contain a mix of sensitive analog circuitry, digital core logic, and high speed
I/O circuitry. The PCB’s design is part of the system circuit for all of these subsystems that can either enhance or detract
from desired operation.
General issues such as placement and stack up are covered. Additionally, subsystem issues such as USB 2.0 / 3.1
Gen 1 and Gen 2 signaling/impedance, crystal connections, and other critical circuits are discussed. Controlling EMI,
system power distribution, and signal return path management will also be addressed.
The guidelines presented supersede earlier notes for the applicable devices. The following recommendations are based
on Microchip’s experience and knowledge and may be accepted or rejected. Microchip does not guarantee any design.
Each company is ultimately responsible for determining the suitability of its own design.
1.4 References
Data Sheets: USB54xx, USB55xx, USB56xx,USB57xx, USB58xx, USB59xx, USB7xxx, USB8xxx, USB38xx,
USB25xx and USB46xx USB Hub Controller and Hub-Combo devices
Application Note: AN 26.21
Application Note: AN 18.15
Evaluation designs that are referenced in this document can be found on the Microchip web site.
AN26.2
Implementation Guidelines for Microchip’s USB 2.0 and
USB 3.1 Gen 1 and Gen 2 Hub and Hub-Combo Devices
Author: Carl Johnson
Microchip Technology Inc.
AN26.2
DS00001876C-page 2 2012-2019 Microchip Technology Inc.
2.0 SCHEMATIC GUIDELINES
Specific requirements and suggestions for the schematic implementation of Microchip’s USB hub controllers are indi-
cated in this section. Product data sheets specify basic circuit needs.
2.1 Chassis and Cable Ground
USB hub devices can be implemented in the following ways:
Embedded with a host controller
Embedded with a mix of inaccessible ports with embedded devices and user-accessible ports
Embedded with a mix of a host, inaccessible ports with embedded devices, and user-accessible ports
A stand-alone hub
Each of these implementation details can affect the best method to use for connecting the chassis and USB cable
shields to digital ground. The best way to make these connections will depend on the design’s system details. Refer to
the many reference documents and white papers on this topic available on the Internet, especially those published by
members of the USB consortium and providers of USB-enabled motherboards and devices.
Microchip has observed positive EMI and ESD behavior on stand-alone designs when connecting the USB cable shield
to digital ground with an RC network (330 resistor and a 0.1 F capacitor in parallel) at each USB connector.
2.2 VDD12 and VDD33 Power Regulator
The USB57x4 & USB553x family of hubs use two external power voltages: VDD12 at 1.25 V, and VDD33 at 3.3 V.
The VDD12 rail is used for core digital functions and for the USB 3.1 Gen 1 PHYs. The VDD12 current consumed by
the hub device will vary greatly. When the device is in “suspend” it will consume very little current. It will consume max-
imum current when all USB 3.1 Gen 1 SuperSpeed interfaces are active. The selected regulator must be stable, low
noise, and accurate across all power consumption ranges.
The VDD33 rail for the USB57x4 & USB553x devices are used by the PLL and other circuitry. Additionally, USB25xx
devices derive core and other rails from VDD33. Therefore, the VDD33 supply must be very clean. Noise on VDD33
must be filtered out before it is received by the hub device. Some systems require < 5 mV of ripple on VDD33 at the hub
device pins to pass SSC certification of suite. Switching regulators are a common source for the USB 3.1 Gen 1 test
VDD33 noise. The example in Figure 2 shows an effective filter to block switching regulator noise from VDD33.
FIGURE 1: EXAMPLE CHASSIS GROUND CONNECTION


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Model: USB3613

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