Microchip WFI32E02UE Manual
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© 2020 Microchip Technology Inc. DS60001192D-page 50-1
Section 50. CPU for Devices with MIPS32® microAptiv™
and M-Class Cores
This section of the manual contains the following topics:
50.1 Introduction .................................................................................................................. 50-2
50.2 Architecture Overview.................................................................................................. 50-4
50.3 PIC32 CPU Details ...................................................................................................... 50-8
50.4 Special Considerations When Writing to CP0 Registers ........................................... 50-13
50.5 MIPS32 Architecture .................................................................................................. 50-14
50.6 CPU Bus .................................................................................................................... 50-15
50.7 Internal System Busses ............................................................................................. 50-15
50.8 Set/Clear/Invert .......................................................................................................... 50-16
50.9 ALU Status Bits.......................................................................................................... 50-16
50.10 Interrupt and Exception Mechanism .......................................................................... 50-17
50.11 Programming Model................................................................................................... 50-17
50.12 Floating Point Unit (FPU) ........................................................................................... 50-24
50.13 Coprocessor 0 (CP0) Registers ................................................................................. 50-42
50.14 Coprocessor 1 (CP1) Registers ............................................................................... 50-121
50.15 microMIPS Execution............................................................................................... 50-132
50.16 MCU ASE Extension ................................................................................................ 50-132
50.17 MIPS DSP ASE Extension ....................................................................................... 50-133
50.18 Memory Model (MCU only) ...................................................................................... 50-133
50.19 Memory Management (MPU only) ........................................................................... 50-135
50.20 L1 Caches (MPU only)............................................................................................. 50-141
50.21 CPU Instructions...................................................................................................... 50-145
50.22 MIPS DSP ASE Instructions .................................................................................... 50-151
50.23 CPU Initialization......................................................................................................50-153
50.24 Effects of a Reset.....................................................................................................50-154
50.25 Related Application Notes ........................................................................................ 50-155
50.26 Revision History ....................................................................................................... 50-156
PIC32 Family Reference Manual
DS60001192D-page 50-2 © 2020 Microchip Technology Inc.
50.1 INTRODUCTION
Depending on the device family, PIC32 devices are a complex System-on-Chip (SoC), which are
based on the microAptiv™ Microprocessor core or the M-Class Microprocessor core from
Imagination Technologies Ltd. This document provides an overview of the CPU system
architecture and features of PIC32 microcontrollers that feature these microprocessor cores.
The microAptiv Microprocessor core is a superset of the MIPS
® M14KE™ and M14KEc™
Microprocessor cores. These cores are state of the art, 32-bit, low-power, RISC processor cores
with the enhanced MIPS32® Release 2 Instruction Set Architecture (ISA).
The M-Class Microprocessor core is a superset of the microAptiv™ Microprocessor core. This
32-bit, low-power, RISC processor core uses the enhanced MIPS32
® Release 5 Instruction Set
Architecture (ISA).
Visit the Imagination Technologies Ltd. website (www.imgtec.com) to learn more about the
microprocessor cores.
Depending on the core configuration, one of two options, MCU or MPU, are used, as shown in
Table 50-1.
Table 50-1: microAptiv and M-Class Microprocessor Core Configurations
The primary difference between the MCU and MPU is the presence of an L1 cache and
TLB-based MMU on the MPU. These features are used to facilitate PIC32 designs that use
operating systems to manage virtual memory.
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “CPU” chapter in the current device
data sheet to check whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
MCU Features MPU Features
Split-bus architecture Unified bus architecture
Integrated DSP ASE (see Note 1) Integrated DSP ASE (see Note 1)
Integrated MCU™ ASE Integrated MCU ASE
microMIPS™ code compression microMIPS code compression
FMT-based MMU TLB-based MMU (see Note 1)
Two shadow register sets Eight shadow register sets
EJTAG TAP controller EJTAG TAP controller
Performance counters Performance counters
Hardware Trace (iFlowtrace®) Hardware Trace (iFlowtrace)
Level One (L1) CPU cache
Note 1: This feature is not available on all devices, refer to the “CPU” chapter of the spe-
cific device data sheet to determine availability.
© 2020 Microchip Technology Inc. DS60001192D-page 50-3
Section 50. CPU for Devices with MIPS32® microAp-
50.1.1 Key Features Common to All PIC32 Devices with the microAptiv
Microprocessor Core
The following key features are common to all PIC32 devices that are based on the microAptiv
Microprocessor core:
• microMIPS variable-length instruction mode for compact code
• Vectored interrupt controller with up to 256 interrupt sources
• Atomic bit manipulations on peripheral registers (Single cycle)
• High-speed Microchip ICD port with hardware-based non-intrusive data monitoring and
application data streaming functions
• EJTAG debug port allows extensive third party debug, programming and test tools support
• Instruction controlled power management modes
• Five-stage pipelined instruction execution
• Internal code protection to help protect intellectual property
• Arithmetic saturation and overflow handling support
• Zero cycle overhead saturation and rounding operations
• Atomic read-modify-write memory-to-memory instructions
• MAC instructions with up to 4 accumulators
• Native fractional data type (Q15, Q31) with rounding support
• Digital Signal Processing (DSP) Application-Specific Extension (ASE) Revision 2, which adds
DSP capabilities with support for powerful data processing operations
• Multiply/Divide unit with a maximum issue rate of one 32 x 32 multiply per clock
50.1.2 Key Features Common to All PIC32 Devices with the M-Class
Microprocessor Core
In addition to the features described for devices with the microAptiv core, the following key
features are common to all PIC32 devices that are based on the M-Class Microprocessor core:
• Implements the latest MIPS Release 5 Architecture, which includes IP protection and
reliability for industrial controllers, Internet of Things (IoT), wearables, wireless
communications, automotive, and storage
• Floating Point Unit (FPU)
50.1.3 Related MIPS Documentation
Related MIPS documentation is available for download from the related Imagination
Technologies Ltd. product page. Please note that a login may be required to access these
documents.
Documentation for the microAptiv core is available for download at:
http://www.imgtec.com/mips/aptiv/microaptiv.asp
Documentation for the M-Class core is available for download at:
http://www.imgtec.com/mips/warrior/mclass.asp
PIC32 Family Reference Manual
DS60001192D-page 50-4 © 2020 Microchip Technology Inc.
50.2 ARCHITECTURE OVERVIEW
The PIC32 family of devices are complex systems-on-a-chip that contain many features.
Included in all processors of the PIC32 family is a high-performance RISC CPU, which can be
programmed in 32-bit and 16-bit modes, and even mixed modes.
Devices with the M-Class core include a Floating Point Unit (FPU) that implements the MIPS
Release 5 Instruction Set Architecture for floating point computation. The FPU implementation
supports the ANSI/IEEE Standard 754 (IEEE Standard for Binary Floating-Point Arithmetic) for
single- and double-precision data formats.
PIC32 devices contain a high-performance Interrupt Controller, DMA controller, USB controller,
in-circuit debugger, a high-performance switching matrix for high-speed data accesses to the
peripherals, and on-chip data RAM memory, which holds data and programs. The optional
prefetch cache and prefetch buffer for the Flash memory, which hides the latency of the Flash,
provides zero Wait state equivalent performance.
Figure 50-1: PIC32 Block Diagram
Note: Refer to the “CPU” chapter in the specific device data sheet to determine availabil-
ity of the FPU module in your device.
JTAG/BSCAN Priority Interrupt
Controller LDO VREG
DMAC ICD
PIC32 CPU
System Bus
Prefetch Cache Data RAM
Peripheral
Flash Memory
Flash Controller
Clock Control/
Generation Reset Generation
PMP/PSP
PORTS
ADC
RTCC
Timers
Input Capture
PWM/Output
Compare
Comparators
SSP/SPI
I2C™
UART
128-bit
USB
Bridge
CAN
Motor Control
PWM
DAC
CTMU
ETH
Note: This diagram is provided as a general example. Please refer to the “Device
Overview” chapter in the specific device data sheet to determine availability of
© 2020 Microchip Technology Inc. DS60001192D-page 50-5
Section 50. CPU for Devices with MIPS32® microAp-
The peripherals of a PIC32 device connect to the CPU through a System Bus and a series of
internal busses. The main peripheral bus connects most of the peripheral units to the System Bus
through one or more peripheral bridges.
The PIC32 CPU performs operations under program control. Instructions are fetched by the CPU
and are synchronously decoded and executed. Instructions exist in either Program Flash
memory or Data RAM memory. In addition, PIC32 devices with the microAptiv and M-Class core
incorporate the MIPS DSP Application-Specific Extension Revision 2 that provides digital signal
processing (DSP) capabilities with support for a number of powerful data processing operations.
The PIC32 CPU is based on a load/store architecture and performs most operations on a set of
internal registers. Specific load and store instructions are used to move data between these
internal registers and the outside world.
Figure 50-2: microAptiv™ Microprocessor Core Block Diagram
System
Coprocessor
MDU
(Enhanced MDU with
DSP ASE(3))
L1 Data
Cache(2)
MMU
(FMT or
TLB(1))
TAP
EJTAG
Power
Management
Off-Chip
Debug I/F
Execution Core
(RF/ALU/Shift, DSP ASE(3))
On-Chip
Memory
Trace
Off-Chip
Trace I/F
Memory
Interface Dual Memory
I/F
Note 1: TLB is available only on devices with the MPU Microprocessor core.
2: Level One (L1) caches are available only on devices with the MPU Microprocessor core.
3: DSP ASE is not available on all devices. Refer to the “CPU” chapter in the specific device data sheet to determine
availability.
L1
Instruction
Cache(2)
PIC32 Family Reference Manual
DS60001192D-page 50-10 © 2020 Microchip Technology Inc.
50.3.2 Execution Unit
The PIC32 Execution Unit is responsible for carrying out the processing of most of the instruc-
tions of the MIPS instruction set. The Execution Unit provides single-cycle throughput for most
instructions by means of pipelined execution. Pipelined execution, sometimes referred to as
“pipelining”, is where complex operations are broken into smaller pieces called stages. Operation
stages are executed over multiple clock cycles.
The Execution Unit contains the following features:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction address
• Logic for branch determination and branch target address calculation
• Load aligner
• Bypass multiplexers used to avoid stalls when executing instructions streams where data
producing instructions are followed closely by consumers of their results
• Leading Zero/One detect unit for implementing the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing bit-wise logical operations
• Shifter and Store Aligner
50.3.3 Multiply/Divide Unit (MDU)
The Multiply/Divide unit (MDU) performs multiply and divide operations. The MDU consists of a
32 x 16 multiplier, result-accumulation registers (HI and LO), multiply and divide state machines,
and all multiplexers and control logic required to perform these functions. The high-performance,
pipelined MDU supports execution of a 16 x 16 or 32 x 16 multiply operation every clock cycle;
32 × 32 multiply operations can be issued every other clock cycle. Appropriate interlocks are
implemented to stall the issue of back-to-back 32 x 32 multiply operations. Divide operations are
implemented with a simple 1 bit per clock iterative algorithm and require 35 clock cycles in the
worst case to complete. Any attempt to issue a subsequent MDU instruction while a divide is still
active causes a pipeline stall until the divide operation is completed.
The microprocessor cores implement an additional multiply instruction, MUL, which specifies that
lower 32-bits of the multiply result be placed in the register file instead of the HI/LO register pair.
By avoiding the explicit move from the LO (MFLO) instruction, which required when using the LO
register, and by supporting multiple destination registers, the throughput of multiply-intensive
operations is increased. Two instructions, multiply-add (MADD/MADDU) and multiply-subtract
( /MSUB MSUBU), are used to perform the multiply-add and multiply-subtract operations. The MADD
instruction multiplies two numbers, and then adds the product to the current contents of the HI
and LO registers. Similarly, the MSUB instruction multiplies two operands, and then subtracts the
product from the HI and LO registers. The MADD MADDU/ and MSUB MSUBU/ operations are
commonly used in Digital Signal Processor (DSP) algorithms.
The MDU is a separate pipeline for integer multiply and divide operations and DSP ASE multiply
instructions (see Note). This pipeline operates in parallel with the integer unit (IU) pipeline and
does not stall when the IU pipeline stalls. This allows the long-running MDU operations to be
partially masked by system sta instructions. The MDU supportslls and/or other integer unit
execution of one 32 x 32 multiply or multiply-accumulate operation every clock cycle. The 32-bit
divide operation executes in 12-38 clock cycles. The MDU also implements various shift
instructions operating on the HI/LO register and multiply instructions as defined in the DSP ASE.
50.3.4 Shadow Register Sets
The PIC32 processor implements one or more copies of the General Purpose Registers (GPR)
for use by high-priority interrupts. The extra banks of registers are known as shadow register
sets. When a high-priority interrupt occurs, the processor automatically switches to a shadow
register set without software intervention. This reduces overhead in the interrupt handler and
reduces effective latency.
The shadow register sets are controlled by registers located in the System Coprocessor (CP0)
as well as the interrupt controller hardware located outside of the CPU core.
For more information on shadow register sets, refer to Section 8. “Interrupts” (DS60001108) of
the “PIC32 Family Reference Manual”.
Note: DSP ASE is not available on all devices. Refer to the “CPU” chapter of the specific
device data sheet to determine availability
© 2020 Microchip Technology Inc. DS60001192D-page 50-11
Section 50. CPU for Devices with MIPS32® microAp-
50.3.5 Pipeline Interlock Handling
Smooth pipeline flow is interrupted when an instruction in a pipeline stage cannot advance due
to a data dependency or a similar external condition. Pipeline interruptions are handled entirely
in hardware. These dependencies are referred to as “interlocks”. At each cycle, interlock
conditions are checked for all active instructions. An instruction that depends on the result of a
previous instruction is an example of an interlock condition.
In general, MIPS processors support two types of hardware interlocks:
• Stalls – These interlocks are resolved by halting the entire pipeline. All instructions, cur-
rently executing in each pipeline stage, are affected by a stall.
• Slips – These interlocks allow one part of the pipeline to advance while another part of the
pipeline is held static
In the PIC32 processor core, all interlocks are handled as slips. These slips are minimized by
grabbing results from other pipeline stages by using a method called register bypassing, which
is described in 50.3.6 “Register Bypassing”.
As shown in Figure 50-6, the sub instruction has a source operand dependency on register r3
with the previous add instruction. The sub instruction slips by two clocks waiting until the result
of the add is written back to register r3. This slipping does not occur on the PIC32 family of
processors.
Figure 50-6: Pipeline Slip (If Bypassing Was Not Implemented)
Note: To illustrate the concept of a pipeline slip, the example in Figure 50-6 shows would
happen if the PIC32 core did not implement register bypassing.
EI M W
ESLIPI M A WE
One
Cycle
One
Cycle
One
Cycle
One
Cycle
One
Cycle
One
Cycle
One
Cycle
One
Cycle
A
ESLIP
Add r3, r2, r1
(r r r3 2 + 1
Sub r4, r3, r7
(r r r4 3 – 7
PIC32 Family Reference Manual
DS60001192D-page 50-12 © 2020 Microchip Technology Inc.
50.3.6 Register Bypassing
As mentioned previously, the PIC32 processor implements a mechanism called register bypass-
ing that helps reduce pipeline slips during execution. When an instruction is in the E stage of the
pipeline, the operands must be available for that instruction to continue. If an instruction has a
source operand that is computed from another instruction in the execution pipeline, register
bypassing allows a shortcut to get the source operands directly from the pipeline. An instruction
in the E stage can retrieve a source operand from another instruction that is executing in either
the M stage or the A stage of the pipeline. As seen in Figure 50-7, a sequence of three instruc-
tions with interdependencies does not slip at all during execution. This example uses both A to
E, and M to E register bypassing. Figure 50-8 shows the operation of a load instruction utilizing
A to E bypassing. Since the result of load instructions are not available until the A pipeline stage,
M to E bypassing is not needed.
The performance benefit of register bypassing is that instruction throughput is increased to the
rate of one instruction per clock for ALU operations, even in the presence of register
dependencies.
Figure 50-7: IU Pipeline M to E Bypass
Figure 50-8: IU Pipeline A to E Data Bypass
EI M W
EI WA
One
Cycle
One
Cycle
One
Cycle
One
Cycle
One
Cycle
One
Cycle
A
M
Add1
r r r3 = 2 + 1
Sub2
r r r4 = 3 – 7
Add3
r r r5 = 3 + 4 EI AM
M to E Bypass A to E Bypass
M to E Bypass
EI M W
EI WA
One
Cycle One
Cycle One
Cycle One
Cycle One
Cycle One
Cycle
A
M
Load Instruction
Consumer of Load Data Instruction EI AM
Data Bypass from A to E
One Clock
Load Delay
© 2020 Microchip Technology Inc. DS60001192D-page 50-13
Section 50. CPU for Devices with MIPS32® microAp-
50.4 SPECIAL CONSIDERATIONS WHEN WRITING TO CP0 REGISTERS
In general, the PIC32 core ensures that instructions are executed following a fully sequential pro-
gram model. Each instruction in the program sees the results of the previous instruction. There
are some deviations to this model. These deviations are referred to as “hazards”.
In privileged software, there are two hazards:
• Execution
• Instruction
50.4.1 Execution Hazards
Execution hazards are those created by the execution of one instruction, and seen by the
execution of another instruction. Table 50-2 lists the execution hazards.
Table 50-2: Execution Hazards
50.4.2 Instruction Hazards
Instruction hazards are those created by the execution of one instruction, and seen by the
instruction fetch of another instruction. Table 50-3 lists the instruction hazards.
Table 50-3: Instruction Hazards
Created by Seen by Hazard On Spacing
(Instructions)
LL MFC0 LLAddr 1
MTC0 Coprocessor instruction execution
depends on the new value of the CU0 bit
(Status[28])
CU0 bit (Status[28]) 1
MTC0 ERET EPC, DEPC, ErrorEPC 1
MTC0 DI, EI, Interrupted Instruction IE bit (Status[0]) 1
MTC0 Interrupted Instruction IP1 and IP0 bits (Cause[1] and [0]) 3
MTC0 TLBR TLBWI TLBWR, , EntryHi 1
MTC0 TLBP, Load/Store affected by new state ASID[7:0] bits (EntryHi[7:0]) 1
MTC0 TLBWI TLBWR, Index 1
MTC0 RDPGPR WRPGPR, PSS[3:0] bits (SRSCtl[9:6]) 1
MTC0 Instruction is not seeing a core timer
interrupt
Compare update that clears the core
timer Interrupt
4
MTC0 Instruction affected by change Any other CP0 register 2
Created by Seen by Hazard On Spacing
(Instructions)
TLBWR TLBWI, Instruction fetch using new TLB entry TLB entry 3
MTC0 Instruction fetch seeing the new value
(including a change to ERL followed by an
instruction fetch from the useg segment)
Status
MTCO Instruction fetch seeing the new value ASID[7:0] bits (EntryHi[7:0]) 3
MTC0 Instruction fetch seeing the new value WatchHi and WatchLo 1
MTC0 Interrupted instruction IP1 and IP0 bits
(Cause[1] and [0])
2
Instruction
stream write via
cache
Instruction fetch seeing the new instruction
stream
Cache entries 3
Instruction
stream write via
store
Instruction fetch seeing the new instruction
stream
Cache entries System
dependent
© 2020 Microchip Technology Inc. DS60001192D-page 50-17
Section 50. CPU for Devices with MIPS32® microAp-
50.10 INTERRUPT AND EXCEPTION MECHANISM
The PIC32 family of processors implement an efficient and flexible interrupt and exception han-
dling mechanism. Interrupts and exceptions both behave similarly in that the current instruction
flow is changed temporarily to execute special procedures to handle an interrupt or exception.
The difference between the two is that interrupts are usually a result of normal operation, and
exceptions are a result of error conditions such as bus errors.
When an interrupt or exception occurs, the processor does the following:
1. The PC of the next instruction to execute after the handler returns is saved into a
coprocessor register.
2. The Cause register is updated to reflect the reason for exception or interrupt.
3. The Status register EXL or ERL bit is set to cause Kernel mode execution.
4. Handler PC is calculated from Ebase and OFFSET values.
5. Automated Interrupt Epilogue can save some of the COP0 state in the stack and
automatically update some of the COP0 registers in preparation for interrupt handling.
6. Processor starts execution from new PC.
This is a simplified overview of the interrupt and exception mechanism. Refer to the “CPU
Exceptions and Interrupt Controller” chapter in the specific device data sheet for details.
50.11 PROGRAMMING MODEL
The PIC32 family of processors is designed to be used with a high-level language such as the C
programming language. It supports several data types and uses simple but flexible addressing
modes needed for a high-level language. There are 32 General Purpose Registers and two
special registers for multiplying and dividing.
There are three different formats for the machine language instructions on the PIC32 processor:
• Immediate or I-type CPU instructions
• Jump or J-type CPU instructions, and
• Registered or R-type CPU instructions
Most operations are performed in registers. The register type CPU instructions have three
operands; two source operands and a destination operand.
Having three operands and a large register set allows assembly language programmers and
compilers to use the CPU resources efficiently. This creates faster and smaller programs by
allowing intermediate results to stay in registers rather than constantly moving data to and from
memory.
The immediate format instructions have an immediate operand, a source operand and a desti-
nation operand. The jump instructions have a 26-bit relative instruction offset field that is used to
calculate the jump destination.
Note: In this section, the terms “precise” and “imprecise” are used to describe exceptions.
A precise exception is one in which the EPC (CP0, Register 14, Select 0) can be
used to identify the instruction that caused the exception. For imprecise exceptions,
the instruction that caused the exception cannot be identified. Most exceptions are
precise. Bus error exceptions may be imprecise.
© 2020 Microchip Technology Inc. DS60001192D-page 50-19
Section 50. CPU for Devices with MIPS32® microAp-
50.11.2 CPU Registers
The PIC32 architecture defines the following CPU registers:
• Thirty-two 32-bit General Purpose Registers (GPRs)
• The standard MIPS32 architecture defines one pair of HI/LO accumulator registers (AC0).
The cores in PIC32 devices include the DSP ASE (see Note), which provides three addi-
tional pairs of HI/LO accumulator registers (AC1, AC2, and AC3). These registers improve
the parallelization of independent accumulation routines. DSP instructions that target the
accumulators use two instruction bits to specify the destination accumulator.
• A special purpose program counter (PC), which is affected only indirectly by certain
instructions; it is not an architecturally visible register.
50.11.2.1 CPU GENERAL PURPOSE REGISTERS
Two of the CPU General Purpose Registers have assigned functions:
• r0 – This register is hard-wired to a value of ‘0’, and can be used as the target register for
any instruction the result of which will be discarded. r0 can also be used as a source when
a ‘0’ value is needed.
• r31 – This is the destination register used by JAL, BLTZAL, BLTZALL, BGEZAL, and
BGEZALL, without being explicitly specified in the instruction word; otherwise, r31 is used
as a normal register.
The remaining registers are available for general purpose use.
50.11.2.2 REGISTER CONVENTIONS
Although most of the registers in the PIC32 architecture are designated as General Purpose
Registers, as shown in Table 50-5, there are some recommended uses of the registers for correct
software operation with high-level languages such as the Microchip MPLAB
® XC32 C/C++
compiler.
Table 50-5: Register Conventions
Note: DSP ASE is not available on all devices. Please consult the “CPU” chapter of the
specific device data sheet to determine availability
CPU
Register
Symbolic
Register Usage
r0 zero Always ‘0’ (see Note 1)
r1 at Assembler Temporary
r2 - r3 v0-v1 Function Return Values
r4 - r7 a0-a3 Function Arguments
r8 - r15 t0-t7 Temporary – Caller does not need to preserve contents
r16 - r23 s0-s7 Saved Temporary – Caller must preserve contents
r24 - r25 t8-t9 Temporary – Caller does not need to preserve contents
r26 - r27 k0-k1 Kernel temporary – Used for interrupt and exception handling
r28 gp Global Pointer – Used for fast-access common data
r29 sp Stack Pointer – Software stack
r30 s8 or fp Saved Temporary – Caller must preserve contents OR
Frame Pointer – Pointer to procedure frame on stack
r31 ra Return Address (see Note 1)
Note 1: Hardware enforced, not just convention.
PIC32 Family Reference Manual
DS60001192D-page 50-20 © 2020 Microchip Technology Inc.
50.11.2.3 CPU SPECIAL PURPOSE REGISTERS
The CPU contains these special purpose registers:
• PC – Program Counter register
• AC0 through AC3 – 64-bit Accumulator register pairs (HI/LO):
- HI/LO – Multiply and divide register pair (high and low result):
• During a multiply operation, the HI and LO registers store the product of integer multiply
• During a multiply-add or multiply-subtract operation, the HI and LO registers store the
result of the integer multiply-add or multiply-subtract
• During a division, the HI and LO registers store the quotient (in LO) and remainder (in
HI) of integer divide
• During a multiply-accumulate, the HI and LO registers store the accumulated result of
the operation
Figure 50-13 shows the layout of the CPU registers.
Figure 50-13: CPU Registers
31 0 31 0
r0 (zero) HI (0)
r1 (at) LO (0)
r2 (v0) HI (1)
r3 (v1) LO (1)
r4 (a0) HI (2)
r5 (a1) LO (2)
r6 (a2) HI (3)
r7 (a3) LO (3)
r8 (t0)
r9 (t1)
r10 (t2)
r11 (t3)
r12 (t4)
r13 (t5)
r14 (t6)
r15 (t7)
r16 (s0)
r17 (s1)
r18 (s2)
r19 (s3)
r20 (s4)
r21 (s5)
r22 (s6)
r23 (s7)
r24 (t8)
r25 (t9)
r26 (k0)
r27 (k1)
r28 (gp)
r29 (sp)
r30 (s8 or fp) 31 0
r31 (ra) PC
General Purpose Registers Special Purpose Registers
Produkt Specifikationer
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