Microchip WFI32E03PC Manual

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Section 50. CPU for Devices with MIPS32® microAptiv™

and M-Class Cores

This section of the manual contains the following topics:

50.1 Introduction .................................................................................................................. 50-2

50.2 Architecture Overview.................................................................................................. 50-4

50.3 PIC32 CPU Details ...................................................................................................... 50-8

50.4 Special Considerations When Writing to CP0 Registers ........................................... 50-13

50.5 MIPS32 Architecture .................................................................................................. 50-14

50.6 CPU Bus .................................................................................................................... 50-15

50.7 Internal System Busses ............................................................................................. 50-15

50.8 Set/Clear/Invert .......................................................................................................... 50-16

50.9 ALU Status Bits.......................................................................................................... 50-16

50.10 Interrupt and Exception Mechanism .......................................................................... 50-17

50.11 Programming Model................................................................................................... 50-17

50.12 Floating Point Unit (FPU) ........................................................................................... 50-24

50.13 Coprocessor 0 (CP0) Registers ................................................................................. 50-42

50.14 Coprocessor 1 (CP1) Registers ............................................................................... 50-121

50.15 microMIPS Execution............................................................................................... 50-132

50.16 MCU ASE Extension ................................................................................................ 50-132

50.17 MIPS DSP ASE Extension ....................................................................................... 50-133

50.18 Memory Model (MCU only) ...................................................................................... 50-133

50.19 Memory Management (MPU only) ........................................................................... 50-135

50.20 L1 Caches (MPU only)............................................................................................. 50-141

50.21 CPU Instructions...................................................................................................... 50-145

50.22 MIPS DSP ASE Instructions .................................................................................... 50-151

50.23 CPU Initialization......................................................................................................50-153

50.24 Effects of a Reset.....................................................................................................50-154

50.25 Related Application Notes ........................................................................................ 50-155

50.26 Revision History ....................................................................................................... 50-156

PIC32 Family Reference Manual

50.3 PIC32 CPU DETAILS

50.3.1 Pipeline Stages

The pipeline consists of these five stages:

• Instruction (I) Stage

• Execution (E) Stage

• Memory (M) Stage

• Align (A) Stage

• Writeback (W) Stage

50.3.1.1 I STAGE – INSTRUCTION FETCH

During I stage:

• An instruction is fetched from the instruction SRAM

• microMIPS instructions are converted into instructions that are similar to MIPS32 instructions

50.3.1.2 E STAGE – EXECUTION

During E stage:

• Operands are fetched from the register file

• Operands from the M and A stage are bypassed to this stage

• The Arithmetic Logic Unit (ALU) begins the arithmetic or logical operation for

• The ALU calculates the data virtual address for load and store instructions and the MMU

performs the fixed virtual-to-physical address translation

• The ALU determines whether the branch condition is true and calculates the virtual branch

target address for branch instructions

• Instruction logic selects an instruction address and the MMU performs the fixed

virtual-to-physical address translation

• All multiply divide operations begin in this stage

50.3.1.3 M STAGE – MEMORY FETCH

During M stage:

• The arithmetic or logic ALU operation completes

• The data SRAM access is performed for load and store instructions

• A 16 x 16 or 32 x 16 MUL operation completes in the array and stalls for one clock in the M

stage to complete the carry-propagate-add in the M stage

• A 32 x 32 MUL operation stalls for two clocks in the M stage to complete the second cycle

of the array and the carry-propagate-add in the M stage

• Multiply and divide calculations proceed in the MDU. If the calculation completes before the

IU moves the instruction past the M stage, the MDU holds the result in a temporary register

until the IU moves the instructions to the A stage (and it is consequently known that it will

not be killed).

50.3.1.4 A STAGE – ALIGN

During A stage:

• A separate aligner aligns loaded data with its word boundary

• A MUL operation makes the result available for writeback. The actual register writeback is

performed in the W stage

• From this stage, load data or a result from the MDU are available in the E stage for

bypassing

50.3.1.5 W STAGE – WRITEBACK

During W stage:

PIC32 Family Reference Manual

50.3.6 Register Bypassing

As mentioned previously, the PIC32 processor implements a mechanism called register bypass-

ing that helps reduce pipeline slips during execution. When an instruction is in the E stage of the

pipeline, the operands must be available for that instruction to continue. If an instruction has a

source operand that is computed from another instruction in the execution pipeline, register

bypassing allows a shortcut to get the source operands directly from the pipeline. An instruction

in the E stage can retrieve a source operand from another instruction that is executing in either

the M stage or the A stage of the pipeline. As seen in Figure 50-7, a sequence of three instruc-

tions with interdependencies does not slip at all during execution. This example uses both A to

E, and M to E register bypassing. Figure 50-8 shows the operation of a load instruction utilizing

A to E bypassing. Since the result of load instructions are not available until the A pipeline stage,

M to E bypassing is not needed.

The performance benefit of register bypassing is that instruction throughput is increased to the

rate of one instruction per clock for ALU operations, even in the presence of register

dependencies.

Figure 50-7: IU Pipeline M to E Bypass

Figure 50-8: IU Pipeline A to E Data Bypass

EI M W

EI WA

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

Add1

r r r3 = 2 + 1

Sub2

r r r4 = 3 – 7

Add3

r r r5 = 3 + 4 EI AM

M to E Bypass A to E Bypass

M to E Bypass

EI M W

EI WA

One

Cycle One

Cycle

Load Instruction

Consumer of Load Data Instruction EI AM

Data Bypass from A to E

One Clock

Load Delay

PIC32 Family Reference Manual

50.11.1 CPU Instruction Formats

A CPU instruction is a single 32-bit aligned word. The CPU instruction formats are:

• Immediate (see Figure 50-10)

• Jump (see Figure 50-11)

• Register (see Figure 50-12)

Table 50-4 describes the fields used in these instructions.

Table 50-4: CPU Instruction Format Fields

Figure 50-10: Immediate (I-Type) CPU Instruction Format

Figure 50-11: Jump (J-Type) CPU Instruction Format

Figure 50-12: Register (R-Type) CPU Instruction Format

Field Description

opcode 6-bit primary operation code.

rd 5-bit specifier for the destination register.

rs 5-bit specifier for the source register.

rt 5-bit specifier for the target (source/destination) register or used to specify

functions within the primary opcode REGIMM.

immediate 16-bit signed immediate used for logical operands, arithmetic signed operands,

load/store address byte offsets, and PC-relative branch signed instruction

displacement.

instr_index 26-bit index shifted left two bits to supply the low-order 28 bits of the jump

target address.

sa 5-bit shift amount.

function 6-bit function field used to specify functions within the primary opcode

SPECIAL.

31 26 25 21 20 16 15 0

opcode rs rt immediate

6 5 5 16

31 26 25 21 20 16 15 11 10 6 5 0

opcode instr_index

6 26

31 26 25 21 20 16 15 11 10 6 5 0

opcode rs rt rd sa function

6 5 5 5 5 6

Section 50. CPU for Devices with MIPS32® microAp-

Table 50-6: microMIPS 16-bit Instruction Register Usage

Table 50-7: microMIPS Special Registers

16-bit

Encoding

32-bit MIPS

Encoding

Symbolic

Name Description

0 16/0 s0/zero General-purpose register

1 17 s1 General-purpose register

2 2 v0 General-purpose register

3 3 v1 General-purpose register

4 4 a0 General-purpose register

5 5 a1 General-purpose register

6 6 a2 General-purpose register

7 7 a3 General-purpose register

N/A 28 gp microMIPS implicitly referenced

General-pointer register

N/A 29 sp microMIPS implicitly referenced Stack

pointer register

N/A 31 ra microMIPS implicitly referenced Return

address register

Symbolic

Name Purpose

PC Program counter. The PC-relative instructions can access this register as an

operand.

HI Contains high-order word of multiply or divide result.

LO Contains low-order word of multiply or divide result.

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Model:	WFI32E03PC

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