Texas Instruments SN74ALS541N Manual

Texas Instruments Ikke kategoriseret SN74ALS541N

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SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025D – APRIL 1982 – REVISED MARCH 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-State Outputs Drive Bus Lines or Buer
Memory Address Registers
pnp Inputs Reduce dc Loading
Data Flowthrough Pinout (All Inputs on
Opposite Side From Outputs)
description
These octal buers and line drivers are designed
to have the performance of the popular
SN54ALS240A/SN74ALS240A series and, at
the same time, oer a pinout with inputs and
outputs on opposite sides of the package. This
arrangement greatly facilitates printed circuit
board layout.
The 3-state control gate is a 2-input NOR gate
such that, if either output-enable (OE1 or OE2)
input is high, all eight outputs are in the
high-impedance state.
The SN74ALS540 provides inverted data. The
’ALS541 provide true data at the outputs.
The -1 versions of SN74ALS540 and
SN74ALS541 are identical to the standard
versions, except that the recommended
maximum IOL is increased to 48 mA. There is no
-1 version of the SN54ALS541.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ALS541 . . . J PACKAGE
SN74ALS540 . . . DW, N, OR NS PACKAGE
SN74ALS541 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
SN54ALS541 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Y1
Y2
Y3
Y4
Y5
A3
A4
A5
A6
A7
A2
A1
OE1
Y7
Y6 OE2
A8
GND
Y8
V
CC
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025D – – APRIL 1982 REVISED MARCH 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SN74ALS540N SN74ALS540N
PDIP N
Tube
SN74ALS540-1N SN74ALS540-1N
PDIP
–
N
Tube
SN74ALS541N SN74ALS541N
SN74ALS541-1N SN74ALS541-1N
Tube SN74ALS540DW
ALS540
Tape and reel SN74ALS540DWR
ALS540
Tube SN74ALS540-1DW ALS540-1
SOIC – DW Tube SN74ALS541DW
ALS541
0 C°C to 70° Tape and reel SN74ALS541DWR
ALS541
Tube SN74ALS541-1DW
ALS541 1
Tape and reel SN74ALS541-1DWR
ALS541
-
1
Tape and reel SN74ALS540NSR ALS540
SOP NS
SN74ALS540-1NSR ALS540-1
SOP
–
NS
Tape and reel SN74ALS541NSR ALS541
SN74ALS541-1NSR ALS541-1
SSOP DB
Ta
p
e and reel
SN74ALS541DBR G541
SSOP
–
DB
Tape
and
reel
SN74ALS541-1DBR G541-1
55
°
C to 125
°
C
CDIP Tube SNJ54ALS541J SNJ54ALS541J– J
–
55 C°
to
125 C°
LCCC Tube SNJ54ALS541FK SNJ54ALS541FK–
FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
logic diagrams (positive logic)
19
2
1
18
OE1
OE2
A1 Y1
To Seven Other Channels
SN74ALS540 ALS541′
19
2
1
18
OE1
OE2
A1 Y1
To Seven Other Channels
SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025D – – APRIL 1982 REVISED MARCH 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted) †
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg 65 C–°C to 150°. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and”
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not“ ”
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54ALS541 SN74ALS540
SN74ALS541 UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current – –12 15 mA
IOL
Low level out
p
ut current
12 24
mA
I
OL
Low
-
level
output
current
48†
mA
TA Operating free-air temperature –55 125 0 70 C°
†Applies only to the -1 version and only if V
CC is between 4.75 V and 5.25 V
SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025D – – APRIL 1982 REVISED MARCH 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL
tPLH
0.3 V
tPZL
tPZH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B) ≈0 V
VOH
VOL
≈3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
CL
(see Note A) RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t
r = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGE
www.ti.com
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead nish/
Ball material
(6)
MSL Peak Temp
(3)
Op Te
5962-8960201RA ACTIVE CDIP J 20 1 Non-RoHS
& Green
SNPB N / A for Pkg Type -55 t
SN54ALS541J ACTIVE CDIP J 20 1 Non-RoHS
& Green
SNPB N / A for Pkg Type -55 t
SN74ALS540-1N ACTIVE PDIP N 20 20 RoHS &
Non-Green
NIPDAU N / A for Pkg Type 0 to
SN74ALS540-1NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS540DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS540DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS540N ACTIVE PDIP N 20 20 RoHS &
Non-Green
NIPDAU N / A for Pkg Type 0 to
SN74ALS540NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS540NSRG4 ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS541-1DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS541-1N ACTIVE PDIP N 20 20 RoHS &
Non-Green
NIPDAU N / A for Pkg Type 0 to
SN74ALS541-1NE4 ACTIVE PDIP N 20 20 RoHS &
Non-Green
NIPDAU N / A for Pkg Type 0 to
SN74ALS541-1NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS541-1NSRE4 ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS541DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS541DBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS541DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS541DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
PACKAGE
www.ti.com
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead nish/
Ball material
(6)
MSL Peak Temp
(3)
Op Te
SN74ALS541N ACTIVE PDIP N 20 20 RoHS &
Non-Green
NIPDAU N / A for Pkg Type 0 to
SN74ALS541NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS541NSRE4 ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SN74ALS541NSRG4 ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 t
SNJ54ALS541J ACTIVE CDIP J 20 1 Non-RoHS
& Green
SNPB N / A for Pkg Type -55 t
(1) The marketing status values are dened as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in eect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI denes "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in spec
reference these types of products as "Pb-Free".
RoHS Exempt: TI denes "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specic EU RoHS exemption.
Green: TI denes "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based ame retardants meet JS709B low halogen requirements of <=1000ppm th
ame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line i
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead nish/Ball material - Orderable Devices may have multiple material nish options. Finish options are separated by a vertical ruled line. Lead nish/Ball
lines if the nish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its kn
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Eorts are underway to better integrate information fr
PACKAGE
www.ti.com
Addendum-Page 3
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on i
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on a
OTHER QUALIFIED VERSIONS OF SN54ALS541, SN74ALS541 :
•Catalog : SN74ALS541
•Military : SN54ALS541
NOTE: Qualied Version Denitions:
•Catalog - TI's standard catalog product
•Military - QML certied for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
SN74ALS540-1NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74ALS540DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74ALS540NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74ALS541-1NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74ALS541DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74ALS541DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74ALS541NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74ALS540-1N N PDIP 20 20 506 13.97 11230 4.32
SN74ALS540DW DW SOIC 20 25 507 12.83 5080 6.6
SN74ALS540N N PDIP 20 20 506 13.97 11230 4.32
SN74ALS541-1DW DW SOIC 20 25 507 12.83 5080 6.6
SN74ALS541-1N N PDIP 20 20 506 13.97 11230 4.32
SN74ALS541-1NE4 N PDIP 20 20 506 13.97 11230 4.32
SN74ALS541DW DW SOIC 20 25 507 12.83 5080 6.6
SN74ALS541N N PDIP 20 20 506 13.97 11230 4.32
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.38
0.22
8.2
7.4 TYP
SEATING
PLANE
0.05 MIN
0.25
GAGE PLANE
0 -8
2 MAX
B5.6
5.0
NOTE 4
A
7.5
6.9
NOTE 3
0.95
0.55
(0.15) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
1
10
11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold ash, protrusions, or gate burrs. Mold ash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead ash. Interlead ash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
A 15
DETAIL A
TYPICAL
SCALE 2 .0 00
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may oer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have dierent recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20

Produkt Specifikationer

Mærke: Texas Instruments
Kategori: Ikke kategoriseret
Model: SN74ALS541N
Type: Logisk kredsløb
Bredde: 26.92 mm
Dybde: 6.6 mm
Højde: 4.57 mm
Antal pr. pakke: 20 stk
Pakkedybde: 506 mm
Pakkebredde: 13.97 mm
Pakkehøjde: 11.23 mm
Opbevaringstemperatur (T-T): -65 - 150 °C
Driftstemperatur (T-T): 0 - 70 °C
Pakketype: PDIP
Antal stifter: 20
Bredde (med stifter): 26.92 mm
Højde (med stifter): 8.26 mm
Dybde (med stifter): 10.92 mm

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