User Guide
© 2023 Microchip Technology Inc. and its subsidiaries
DS50003625A - 1
Introducon (Ask a Queson)
When creating a design using an IGLOO2 device, if you use any of the two DDR controllers (FDDR or MDDR)
or Serial High speed controller (SERDESIF) blocks, you must initialize the conguration registers of these blocks
at run-time before they can be used. For example, for the DDR controller, you must set the DDR mode (DDR3/
DDR2/LPDDR), PHY width, burst mode and ECC. Similarly, for the SERDESIF block used as a PCIe endpoint, you
must set the PCIE BAR to AXI (or AHB) window.
In this document, we describe all the steps necessary to create a Libero design that automatically initializes the
DDR controller and SERDESIF blocks at power up, with the Standalone Initialization mode ON.
First we provide a detailed description of the theory of operation. We introduce the major components of the
Peripheral Initialization Solution and outline how they interact.
Unlike the normal ow (Standalone Initialization OFF) where the initialization solution is created by the System
Builder, in the case of Standalone Initialization mode ON, the initialization solution has to be put together in
SmartDesign using dierent soft IP cores (mentioned in the latter sections), whether you choose to use System
Builder or not. System Builder will not create any initialization logic for any of the peripherals. You have to build
the initialization logic that sits outside the System Builder block, should you choose to use System Builder at all.
Note that as the name suggests, the standalone initialization logic has to be built separately for each of the
peripherals (DDR/SERDES) used.
Next, we describe how to build designs with the Standalone Initialization mode ON in cases where you choose
to use System Builder and in cases where you choose not to.
In this section we address:
• The creation of the conguration data for DDR controller and SERDESIF conguration registers
• The creation of the FPGA logic required to transfer the conguration data to the dierent ASIC conguration
registers
For complete details about the DDR controller and SERDESIF conguration registers please refer to the UG0447:
SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces User Guide and UG0446: SmartFusion2 and
IGLOO2 FPGA High Speed DDR Interfaces User Guide.
IGLOO2 Standalone Peripheral Inializaon Methodology
User Guide
