Microchip PIC24FJ64GA006 Manual

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© 2008 Microchip Technology Inc. Preliminary DS39713B-page 13-1
Parallel Master
Port (PMP)
13
Section 13. Parallel Master Port (PMP)
HIGHLIGHTS
This section of the manual contains the following major topics:
13.1 Introduction .................................................................................................................. 13-2
13.2 Module Registers......................................................................................................... 13-3
13.3 Slave Port Modes....................................................................................................... 13-11
13.4 Master Port Modes..................................................................................................... 13-16
13.5 Application Examples................................................................................................. 13-27
13.6 Operation in Power Save Modes ............................................................................... 13-30
13.7 AC Electrical Specifications ....................................................................................... 13-31
13.8 Register Maps ............................................................................................................ 13-34
13.9 Related Application Notes.......................................................................................... 13-35
13.10 Revision History ......................................................................................................... 13-36
PIC24F Family Reference Manual
DS39713B-page 13-2 Preliminary © 2008 Microchip Technology Inc.
13.1 INTRODUCTION
The Parallel Master Port (PMP) is a parallel, 8-bit I/O module specifically designed to
communicate with a wide variety of parallel devices, such as communications peripherals, LCDs,
external memory devices and microcontrollers. Because the interface to parallel peripherals
varies significantly, the PMP module is highly configurable.
Key features of the PMP module include:
• 8 Data Lines
• Up to 16 Programmable Address Lines
• Up to 2 Chip Select Lines
• Programmable Strobe Options:
- individual read and write strobes, or
- read/write strobe with enable strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port (PSP) Support
• Enhanced Parallel Slave Support:
- address support
- 4-byte deep auto-incrementing buffer
• Programmable Wait States
Figure 13-1: PMP Module Pinout and Connections to External Devices
PMA0
PMA14
PMA15
PMBE
PMRD
PMWR
PMD<7:0>
PMENB
PMRD/PMWR
PMCS1
PMA1
PMA<13:2>
PMALL
PMALH
PMA<7:0>
PMA<15:8>
PMCS2
EEPROM
Address Bus
Data Bus
Control Lines
PIC24F
LCD FIFO
Microcontroller
8-Bit Data (with or without multiplexed addressing)
Up to 16-Bit Address
Parallel Master Port
Buffer

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Model: PIC24FJ64GA006

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