PIC32 Family Reference Manual
DS60001192D-page 50-2 © 2020 Microchip Technology Inc.
50.1 INTRODUCTION
Depending on the device family, PIC32 devices are a complex System-on-Chip (SoC), which are
based on the microAptiv™ Microprocessor core or the M-Class Microprocessor core from
Imagination Technologies Ltd. This document provides an overview of the CPU system
architecture and features of PIC32 microcontrollers that feature these microprocessor cores.
The microAptiv Microprocessor core is a superset of the MIPS
®
M14KE™ and M14KEc™
Microprocessor cores. These cores are state of the art, 32-bit, low-power, RISC processor cores
with the enhanced MIPS32
®
Release 2 Instruction Set Architecture (ISA).
The M-Class Microprocessor core is a superset of the microAptiv™ Microprocessor core. This
32-bit, low-power, RISC processor core uses the enhanced MIPS32
®
Release 5 Instruction Set
Architecture (ISA).
Visit the Imagination Technologies Ltd. website (www.imgtec.com) to learn more about the
microprocessor cores.
Depending on the core configuration, one of two options, MCU or MPU, are used, as shown in
Table 50-1.
Table 50-1: microAptiv and M-Class Microprocessor Core Configurations
The primary difference between the MCU and MPU is the presence of an L1 cache and
TLB-based MMU on the MPU. These features are used to facilitate PIC32 designs that use
operating systems to manage virtual memory.
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “CPU” chapter in the current device
data sheet to check whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
MCU Features MPU Features
Split-bus architecture Unified bus architecture
Integrated DSP ASE (see Note 1) Integrated DSP ASE (see Note 1)
Integrated MCU™ ASE Integrated MCU ASE
microMIPS™ code compression microMIPS code compression
FMT-based MMU TLB-based MMU (see Note 1)
Two shadow register sets Eight shadow register sets
EJTAG TAP controller EJTAG TAP controller
Performance counters Performance counters
Hardware Trace (iFlowtrace
®
) Hardware Trace (iFlowtrace)
Level One (L1) CPU cache
Note 1: This feature is not available on all devices, refer to the “CPU” chapter of the spe-
cific device data sheet to determine availability.
