Texas Instruments CD74HC533E Manual

Texas Instruments Ikke kategoriseret CD74HC533E

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Side 1/17
1
Data sheet acquired from Harris Semiconductor
SCHS187C
Features
• Common Latch-Enable Control
• Common Three-State Output Enable Control
• Buered Inputs
• Three-State Outputs
• Bus Line Driving Capacity
• Typical Propagation Delay = 13ns at V
CC = 5V,
CL = 15pF, TA = 25oC (Data to Output)
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤µ1 A at VOL, VOH
Description
The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are
high-speed Octal Transparent Latches manufactured with
silicon gate CMOS technology. They possess the low power
consumption of standard CMOS integrated circuits, as well as
the ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch
enable (LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the
three-state outputs. When the output enable (OE) is high the
outputs are in the high impedance state. The latch operation
is independent of the state of the output enable.
The ’HC533 and ’HCT533 are identical in function to the
’HC563 and CD74HCT563 but have different pinouts. The
’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373;
the latter are non-inverting types.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC) PACKAGE
CD54HC533F3A -55 to 125 20 Ld CERDIP
CD54HC563F3A -55 to 125 20 Ld CERDIP
CD54HCT533F3A -55 to 125 20 Ld CERDIP
CD74HC533E -55 to 125 20 Ld PDIP
CD74HC563E -55 to 125 20 Ld PDIP
CD74HC563M -55 to 125 20 Ld SOIC
CD74HCT533E -55 to 125 20 Ld PDIP
CD74HCT563E -55 to 125 20 Ld PDIP
CD74HCT563M -55 to 125 20 Ld SOIC
January 1998 - Revised July 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54/74HC533, CD54/74HCT533,
CD54/74HC563, CD74HCT563
High-Speed CMOS Logic Octal Inverting
Transparent Latch, Three-State Outputs
[ /Title
(CD74H
C533,
CD74H
CT533,
CD74H
C563,
CD74H
CT563)
/Subject
(High
Speed
2
Pinouts
CD54HC533, CD54HCT533
(CERDIP)
CD74HC533, CD74HCT533
(PDIP)
TOP VIEW
CD54HC563
(CERDIP)
CD74HC563, CD74HCT563
(PDIP, SOIC)
TOP VIEW
Functional Block Diagram
HC/HCT533
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
VCC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
LE 11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
VCC
Q1
Q2
Q3
Q0
Q4
Q5
Q6
Q7
LE
O0
D0
LE
OE
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
D
G
O D
G
O D
G
O D
G
O D
G
O D
G
O D
G
O D
G
O
TRUTH TABLE
OUTPUT ENABLE LATCH ENABLE DATA Q OUTPUT
L H H L
L H L H
L L l H
L L h L
H X X Z
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior to
the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563

Produkt Specifikationer

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Kategori: Ikke kategoriseret
Model: CD74HC533E

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