Texas Instruments CD74HCT299M Manual

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Side 1/20

Data sheet acquired from Harris Semiconductor

SCHS178C

Features

• Buered Inputs

• Four Operating Modes: Shift Left, Shift Right, Load

and Store

• Can be Cascaded for N-Bit Word Lengths

• I/O0 - I/O7 Bus Drive Capability and Three-State for

Bus Oriented Applications

• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA= 25oC

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤µ1 A at VOL, VOH

Pinout

CD54HC299, CD54HCT299

(CERDIP)

CD74HC299, CD74HCT299

(PDIP, SOIC)

TOP VIEW

Description

The ’HC259 and ’HCT299 are 8-bit shift/storage registers

with three-state bus interface capability. The register has four

synchronous-operating modes controlled by the two select

inputs as shown in the mode select (S0, S1) table. The mode

select, the serial data (DS0, DS7) and the parallel data (I/O

- I/O7 ) respond only to the low-to-high transition of the clock

(CP) pulse. S0, S1 and data inputs must be stable one set-

up time prior to the clock positive transition.

The Master Reset ( MR) is an asynchronous active low input.

When MR output is low, the register is cleared regardless of

the status of all other inputs. The register can be expanded

by cascading same units by tying the serial output (Q0) to

the serial data (DS7) input of the preceding register, and

tying the serial output (Q7) to the serial data (DS0) input of

the following register. Recirculating the (n x 8) bits is

accomplished by tying the Q7 of the last stage to the DS0 of

the ﬁrst stage.

The three-state input/output I(/O) port has three modes of

operation:

1. Both output enable ( OE1 and OE2) inputs are low and S0

or S1 or both are low, the data in the register is presented

at the eight outputs.

2. When both S0 and S1 are high, I/O terminals are in the

high impedance state but being input ports, ready for par-

allel data to be loaded into eight registers with one clock

transition regardless of the status of OE1 and OE2.

3. Either one of the two output enable inputs being high will

force I/O terminals to be in the o-state. It is noted that

each I/O terminal is a three-state output and a CMOS

buer input.

1S0

OE1

OE2

I/O6

I/O4

I/O2

I/O0

GND

VCC

DS7

I/O

DS0

Ordering Information

PART NUMBER TEMP. RANGE (o C) PACKAGE

CD54HC299F3A -55 to 125 20 Ld CERDIP

CD54HCT299F3A -55 to 125 20 Ld CERDIP

CD74HC299E -55 to 125 20 Ld PDIP

CD74HC299M -55 to 125 20 Ld SOIC

CD74HC299M96 -55 to 125 20 Ld SOIC

CD74HCT299E -55 to 125 20 Ld PDIP

CD74HCT299M -55 to 125 20 Ld SOIC

CD74HCT299M96 -55 to 125 20 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

January 1998 - Revised May 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC299, CD74HC299,

CD54HCT299, CD74HCT299

High-Speed CMOS Logic

8-Bit Universal Shift Register; Three-State

[ /Title

(CD74

HC299

CD74

HCT29

/Sub-

ject

(High

Speed

CMOS

Logic

8-Bit

Uni-

versal

Shift

Functional Diagram

MODE SELECT FUNCTION TABLE THREE-STATE I/O PORT OPERATING MODE

FUNCTION

INPUTS INPUTS/OUTPUTS

OE1 OE2 S0 S1 Qn (REGISTER) I/O0 --- I/O7

Read Register L L L X L L

LL L X H H

L L X L L L

L L X L H H

Load Register X X H H Qn = I/On I/On = Inputs

Disable I/O H X X X X (Z)

X H X X X (Z)

TRUTH TABLE

FUNCTION

INPUTS REGISTER OUTPUTS

MR CP S0 S1 DS0 DS7 I/On Q0 Q1 --- Q6 Q7

RESET (CLEAR) L X X X X X X L L --- L L

Shift Right H ↑h l l X X L q0 --- q5q6

H↑h l h X X H q 0 --- q5Q6

Shift Left H ↑l h X l X q1 q2 --- q7L

H↑l h X h X q 1q2 --- q7H

Hold (Do Nothing) H ↑l l X X X q0q1 --- q6q7

Parallel Load H ↑h h X X l L L --- L L

H h h X X h H H --- H H↑

H = Input Voltage High Level, h = Input voltage high one set-up timer prior clock transition; L = Input Voltage Low Level; l = Input voltage

low one set-up time prior to clock transition; qn = Lower case letter indicates the state of the reference output one set-up time prior to clock

transition; X - Voltage level on logic status don’t care; Z = Output in high impedance state, = Low to High Clock Transition.↑

I/O

THREE-STATE

OUTPUTS

I/O

THREE-STATE

OUTPUTS

SHIFT

MODE SELECTION

CP OE1 OE2 MR

12 2 3 9 20

VCC

I/O0

STANDARD

OUTPUT

I/O2

I/O4

I/O6

BUS LINE

OUTPUTS

GND

10 11 18

DS0 DS7

I/O1

STANDARD

OUTPUT

I/O3

I/O5

I/O7

BUS LINE

OUTPUTS

THREE-

STATE

CONTROL

CD54HC299, CD74HC299, CD54HCT299, CD74HCT299

Produkt Specifikationer

Mærke:	Texas Instruments
Kategori:	Ikke kategoriseret
Model:	CD74HCT299M
Type:	Logisk kredsløb
Bredde:	13 mm
Dybde:	7.6 mm
Højde:	2.35 mm
Antal pr. pakke:	25 stk
Pakkedybde:	507 mm
Pakkebredde:	12.83 mm
Pakkehøjde:	5.08 mm
Opbevaringstemperatur (T-T):	-65 - 150 °C
Driftstemperatur (T-T):	-55 - 125 °C
Pakketype:	SOIC
Antal stifter:	20
Bredde (med stifter):	13 mm
Højde (med stifter):	2.65 mm
Dybde (med stifter):	10.63 mm