Texas Instruments CY74FCT573ATSOC Manual

Texas Instruments Ikke kategoriseret CY74FCT573ATSOC

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CY54FCT573T, CY74FCT573T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS068 – OCTOBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function and Pinout Compatible With FCT
and F Logic
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Signicantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
3-State Outputs
CY54FCT573T
– 32-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT573T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the
latch-enable (LE) input is high, the ip-ops appear transparent to the data. Data that meets the required setup
times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE )
input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered
into the latches. The ’FCT573T devices are identical to the ’FCT373T devices, except for the ow-through
pinout of the ’FCT573T, which simplifies board design.
These devices are fully specied for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CY54FCT573T . . . D PACKAGE
CY74FCT573T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
VCC
O0
O1
O2
O3
O4
O5
O6
O7
LE
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CY54FCT573T, CY74FCT573T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS068 – OCTOBER 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGE†SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP – Q Tape and reel 4.7 CY74FCT573CTQCT FCT573C
SOIC SO
Tube 4.7 CY74FCT573CTSOC
FCT573C
SOIC
–
SO
Tape and reel 4.7 CY74FCT573CTSOCT
FCT573C
DIP Tube 5.2 CY74FCT573ATPC CY74FCT573ATPC– P
40 C to 85 C
QSOP – Q Tape and reel 5.2 CY74FCT573ATQCT FCT573A
–
40 C°
to
85 C°
SOIC SO
Tube 5.2 CY74FCT573ATSOC
FCT573A
SOIC
–
SO
Tape and reel 5.2 CY74FCT573ATSOCT
FCT573A
QSOP – Q Tape and reel 8 CY74FCT573TQCT FCT573
SOIC SO
Tube 8 CY74FCT573TSOC
FCT573
SOIC
–
SO
Tape and reel 8 CY74FCT573TSOCT
FCT573
– –55 C CDIP °C to 125° D Tube 8.5 CY54FCT573ATLMB
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS OUTPUT
OE LE D O
L H H H
L H L L
L L X Q0
H X X Z
H = High logic level, L = Low logic level,
X = Don’t care, Z = High-impedance state,
Qn = Previous state of flip flops (Q
n 1–)
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
2
19
LE
D0
CP
DO0
Q

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Model: CY74FCT573ATSOC

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