Texas Instruments SN74F573N Manual

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Side 1/5

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SDFS011A − MARCH 1987 − REVISED OCTOBER 1993

2−1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

•Eight Latches in a Single Package

•3-State Bus-Driving True Outputs

•Full Parallel Access for Loading

•Buered Control Inputs

•Package Options Include Plastic

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

description

These 8-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. They are

particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The eight latches of the ′F573 are transparent

D-type latches. While the latch enable (LE) input

is high, the Q outputs follow the data (D) inputs.

When the latch enable is taken low, the Q outputs

are latched at the logic levels set up at the D

inputs.

A buffered output enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or a high-

impedance state. In the high-impedance state, the

outputs neither load nor drive the bus lines

significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines without need for interface or pullup

components.

The output enable (OE) input does not aect the internal operations of the latches. Old data can be retained

or new data can be entered while the outputs are in the high-impedance state.

The SN54F573 is characterized for operation over the full military temperature range of −55° °C to 125 C. The

SN74F573 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each latch)

INPUTS

OUTPUT

OE LE D

OUTPUT

L H H H

L H L L

L L X Q0

H X X Z

GND

VCC

SN54F573 . . . J PACKAGE

SN74F573 . . . DW OR N PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

7Q 1Q

SN54F573 . . . FK PACKAGE

(TOP VIEW)

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

SDFS011A − MARCH 1987 − REVISED OCTOBER 1993

2−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

logic symbol†logic diagram (positive logic)

1D 3

2D 4

4D 6

7D 9

To Seven Other Channels

†This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡

Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) −1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current range −30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the disabled or power-off state −0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state −0.5 V to VCC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state: SN54F573 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74F573 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: SN54F573 −55° °C to 125 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74F573 0° °C to 70 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range −65° °C to 150 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .