Microchip LE79272 Manual

Microchip Ikke kategoriseret LE79272

Læs gratis den danske manual til Microchip LE79272 (86 sider) i kategorien Ikke kategoriseret. Denne vejledning er vurderet som hjælpsom af 14 personer og har en gennemsnitlig bedømmelse på 4.5 stjerner ud af 7.5 anmeldelser. Har du et spørgsmål om Microchip LE79272, eller vil du spørge andre brugere om produktet?

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Side 1/86
Revision Number: 14.0
Issue Date: January 2014
Document Number: 126583
Next Generation Carrier Chipset
Hardware Design Guide
NGCC
Design Guide
Table of Contents
2
Microsemi Corporation Confidential and Proprietary
1.0 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 NGCC Feature Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Physical Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Functional Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 Host Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.2 NGVCP and High Level Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.3 Low Level Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.4 SLAC Peripherals Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.5 Voice DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.6 Low Level Processor and Low Level Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.7 Common Analog Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.8 Digital Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.9 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.10 SLIC-SLAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.0 Hardware Design Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Host Bus Interface - VCP Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 General Purpose Parallel Interface - VCP Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2 Serial Peripheral Interface - VCP Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.3 HBI Timing Requirements - VCP Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Debug Interfaces - VCP Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 HBI/PCM Interface Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Debug Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Host Bus Interface - SLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 SPI on SLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.2 SLAC SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 VCP to SLAC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.1 VCP to SLAC Interface Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5.1 PCM Interface - SLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5.1.1 PCM Transmit Interface - SLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5.1.2 PCM Receive Interface - SLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5.1.3 PCM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5.2 PCM Interface - VCP Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.3 PCM Hardware Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5.3.1 PCM Signal Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6 SLAC-SLIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6.1 RCVP, RCVN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6.2 DCA, DCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6.3 IA, IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6.4 IMT, VIMT, VAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6.5 CANCEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6.6 SVA, SVB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6.7 Battery Supplies and Battery Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6.8 LD, SEL, and P-Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6.9 Debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6.10 Sensitive Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.6.11 SLAC IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.7 EMC Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.8 Using a Single Negative Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.0 Application Circuits and Parts Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
NGCC
Design Guide
Table of Contents
3
Microsemi Corporation Confidential and Proprietary
3.1 Configuration C Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2 Configuration C Parts Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2.1 Factory Calibration with Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2.2 No Calibration with Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.3 No Calibration and No Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3 Configuration D Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.4 Configuration D Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4.1 In-Service Calibration and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5 Configuration E External Ringing Application Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.6 Configuration E External Ringing Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.6.1 Factory Calibration with Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.6.2 No Calibration with Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.6.3 No Calibration and No Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.7 Configuration F External Ringing Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.8 Configuration F External Ringing Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.8.1 In-Service Calibration and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.9 VCP Device Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.9.1 VCP Device Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.0 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.1 PCB Mounting Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.1.1 Le79271 SLIC Thermal Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.1.2 Le79271 SLIC Footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.1.3 Le79272 Dual SLIC Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.1.4 Le79238 LGA Thermal Pad and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2 SLIC Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3 PCB Thermal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.1 Airflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.1.1 Test Platform for Airflow Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.1.2 Electrical Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.3.1.3 Wind Tunnel Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.3.1.4 Thermocouple Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.4 Thermal Resistance and Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.5 Power and Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.6 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.7 EMI Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.0 Power Supply Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.1 +3.3 V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2 +1.8 V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3 Battery Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.1 VBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.2 VBH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.3 VBP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
NGCC
Design Guide
List of Figures
4
Microsemi Corporation Confidential and Proprietary
Figure 1 - 72 Channel NGCC Line Card with Le79124 VCP and Le79272 SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2 - NGCC Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3 - Host Bus Interface Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4 - GPI - 8-bit Parallel Control, Combined Read/Write and Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 - GPI - 8-bit Parallel Control, Separate Read and Write Strobes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6 - GPI - 16-bit Parallel Control, Combined Read/Write and Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 - GPI - 16-bit Parallel Control, Separate Read and Write Strobes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8 - SPI - 4-wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 - Mictor Socket Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 - Series Termination Resistor Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11 - VCP Debug Port - Optional Header Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12 - Host Bus Interface Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13 - 4-wire Master-Slave Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14 - Alternate Master-Slave Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15 - SS Framing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16 - One Data Word Write in Byte Framing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17 - One Data Word Read in Word Framing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18 - Le79234 VCP to SLAC Interface - 32 Channel NGCC Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19 - Le79124 VCP to SLAC Interface - 64 Channel NGCC Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20 - Le79124 VCP to SLAC Interface - 72 Channel NGCC Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21 - Le79128 VCP to SLAC Interface - 128 Channel NGCC Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 22 - Le79234 VCP to SLAC 32-Channel Interface - Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 23 - Le79124 VCP to SLAC 72-Channel Interface - Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 24 - Le79128 VCP to SLAC 128-Channel Interface - Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25 - Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 26 - Hardware Reset for External Ringing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 27 - PCM Highway 8-bit Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 28 - PCM Highway 16-bit Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 29 - SLAC PCM Interface - Highway A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 30 - SLAC PCM Interface - Highway A & B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 31 - VCP-SLAC PCM Interface - 32 Channel NGCC Line Card - Single PCM Highway . . . . . . . . . . . . . . 36
Figure 32 - VCP-SLAC PCM Interface - 64 or 72 Channel NGCC Line Card - Single PCM Highway. . . . . . . . . . 36
Figure 33 - VCP-SLAC PCM Interface - 72 Channel NGCC Line Card - Dual PCM Highways. . . . . . . . . . . . . . . 37
Figure 34 - VCP-SLAC PCM Interface - 72 Channel NGCC Line Card - Two PCM Highways with a Single Clock
and Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 35 - VCP-SLAC PCM Interface - 72 Channel NGCC Line Card - Separate Voice and Test PCM Highways .
39
Figure 36 - VCP-SLAC PCM Interface - 128 Channel NGCC Line Card - Dual PCM Highways. . . . . . . . . . . . . . 40
Figure 37 - SLAC-SLIC Internal Ringing Interface - One Channel Shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 38 - SLAC-SLIC Interface - Sensitive Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 39 - SLAC Open Drain Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 40 - Configuration C - POTS Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 41 - Configuration C - GPON Application (Negative Batteries only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 42 - Configuration C - IVD Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 43 - Configuration D - POTS Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 44 - Configuration D - IVD Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 45 - Configuration E - Battery-Backed Ringing POTS Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 46 - Configuration E - Earth-Backed Ringing POTS Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 47 - Configuration F - Battery-Backed Ringing Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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Figure 48 - Configuration F - Earth-Backed Ringing Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 49 - Le79124 VCP External Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 50 - Le79234 VCP External Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 51 - Le79128 VCP External Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 52 - Recommended PCB Thermal Pad and Via Pattern for 28-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 53 - Recommended PCB Footprint for 28-pin QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 54 - Recommended PCB Thermal Pad and Via Pattern for 48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 55 - Possible SLIC Placement - Hub Arrangement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 56 - Possible SLIC Placement - Slot Arrangement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 57 - Possible Dual SLIC Placement - Hub Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 58 - Le51HR0140 Groupings and Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 59 - Wind Tunnel and Load Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 60 - SLIC Surface Temperature Variation vs. Airflow, Normalized to Inlet Airflow at 22 °C . . . . . . . . . . . . 79
Figure 61 - Power Calculator Example - Supply Currents in Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 62 - Power Calculator Example - Supply Currents in Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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1.0 System Overview
1.1 Introduction
The Next Generation Carrier Chipset (NGCC) implements high line count POTS telephone interfaces, providing a
complete BORSCHT capability for soft switch based Next Generation Networks. NGCC enables the design of
POTS line cards which are DSL friendly, low cost, high performance, and software programmable for multiple
country applications world wide. All AC, DC, and signaling parameters are fully programmable via microprocessor
interfaces. Additionally, the NGCC has self-test and line-test capabilities to resolve faults to the line or line circuit.
This design guide is intended to familiarize the designer with the NGCC system and external interfaces. This guide
provides hardware design, connection, application circuit, parts lists, and layout information. For detailed
information on the functionality provided by the SLIC and SLAC devices, refer to the NGCC Designer’s Guide
document.
As the name suggests, the Hardware Design Guide is to be used as a guide and is not intended to be a substitute
for a system validation. The design is the sole responsibility of the system integrator. Fully evaluate and test the
design prior to deployment.
1.1.1 NGCC Feature Set
• Performs all battery feed, ringing, signalling, hybrid and test functions
• Optimized for Next Generation Broadband xDSL and triple play applications
• Controls state changes to eliminate transients that could cause CRC errors
• Two or three chip solution supports high density, multi-channel architecture
• Supports two negative batteries and one positive battery
• Best-in-class GR-844 equivalent testing capability
• Single hardware design meets multiple country requirements through software programming of:
• Ringing waveform and frequency
• DC loop-feed characteristics and current-limit
• Loop-supervision detection thresholds
• Off-hook debounce circuit
• Ground-key and ring-trip filters
• Off-hook detect de-bounce interval
• Two-wire AC impedance
• Transhybrid balance
• Transmit and receive gains
• Equalization
• Digital I/O pins
• A-law/µ-law and linear selection
• Supports wideband 7.0 kHz mode
• Supports internal battery-backed ringing
• Self-contained ringing generation and control
• Programmed ringing cadence
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• Supports external battery-backed and earth-backed ringing (on ZL79258 SLAC device)
• Programmed ringing cadence and control
• Supports metering generation with envelope shaping
• Programmable metering cadencing
• Smooth polarity reversal
• Automatic CID and signalling and FSK and DTMF modes
• Tone generation
• Call progress tones
• Howler tones
• DTMF tones
• DTMF detection
• Modem support
• Supports both loop-start and ground-start signalling
• HBI and PCM interfaces
• On-hook transmission
• Power/service denial mode
• Line-feed characteristics independent of battery voltage
• Low idle-power per line
• Compatible with inexpensive protection networks
• Monitors two-wire interface voltages and currents for subscriber line diagnostics
• Can monitor and drive the A lead (Tip) and B lead (Ring) independently
• Extremely flexible
• Built-in voice-path test modes
• Integrated self-test features
• Two general purpose I/O pins per channel on SLAC, one specifically configured as a relay driver
• -40 to 85°C operation
• Small physical size
1.2 Physical Partitioning
The NGCC is partitioned into three chip types:
(1) Subscriber Line Interface Chip – – SLIC or NGSLIC Le79271 (single channel) or Le79272 (dual channel)
(2) Subscriber Line Audio Chip – – SLAC or NGSLAC Le79238 (internal ringing) or ZL79258 (internal/external
ringing)
(3) Voice Control Processor – – VCP or NGVCP Le79124 (controls up to 72 channels) or Le79128 (controls up to
128 channels) or Le79234 (controls up to 32 channels). Use of the VCP device is optional.
Device acronyms are used with and without the NG prefix throughout this document.
See Figure 1 for a 72 channel line card block diagram.
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Figure 1 - 72 Channel NGCC Line Card with Le79124 VCP and Le79272 SLIC
1.3 Functional Partitioning
The SLIC is a 150 V device that interfaces to the subscriber telephone line. It provides the power and voltage
necessary to drive a wide variety of telephone lines.
The SLAC device contains channel specific Analog Front End (AFE) blocks, a Common Analog block, channel
specific Digital Front End blocks, a voice DSP block, a Low Level Processor block and a Digital Peripherals block.
An AFE block consists of the ADC and DAC units plus associated buffer circuits necessary to control and monitor
the line voltages, line currents and battery voltages. A Digital Front End block contains the interpolators, decimators
and metering logic. The Common Analog block contains the voltage reference and PLL. The Voice DSP block
handles voice transmission. The Low Level Processor block handles DC feed control, supervision, DTMF detection
and diagnostics front end processing. The Digital Peripherals block contains the control and PCM interfaces of the
Low Level Interface.
The VCP device contains the call control and line diagnostics for the entire line card.
Le79124
VCP
Host Interface
SLAC SLAC
SLAC
SLAC
SLAC
SLAC
SLAC
SLAC
SPI1
bus
PCM
bus
(1 or 2)
SLAC
Network Interface
SPI2
bus
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
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Figure 2 - NGCC Functional Block Diagram
1.3.1 Host Interface
The NGVCP uses the Host Bus Interface (HBI) to communicate with the rest of the system.
SLIC
Analog
Front End
Digital
Front End
SLIC
Analog
Front End
Digital
Front End
Low-Level Software
Low-Level Processor
Common
Analog Voice DSP
SLIC
Analog
Front End
Digital
Front End
SLIC
Analog
Front End
Digital
Front End
Low-Level Software
Low-Level Processor
Common
Analog Voice DSP
Low-Level Interface (MPI)
High-Level Software
1 82 - 7 8N+1 8N+8
Host Bus Interface (HBI)
Protection Protection Protection Protection
SLAC Peripherals SLAC Peripherals
NGVCP
N = 1 to 15
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1.3.6 Low Level Processor and Low Level Software
Besides the codec functions, the integrated voice chip set provides all the sensing, feedback, and clocking
necessary to completely control SLIC device functions with programmable parameters. System-level parameters
under programmable control include active loop current limits, open circuit feed voltages, and loop supervision
thresholds.
The NGCC provides loop supervision capability including off-hook, ring-trip, ground start, and ground-key detection.
Detection thresholds for these functions are programmable. A programmable debounce timer is available that
eliminates false detection due to contact bounce.
For subscriber line diagnostics, AC and DC line conditions can be monitored by connecting analog currents and
voltages to ADCs. This gives the user’s microprocessor the ability to configure the SLIC/SLAC system and make
system and line tests. Both longitudinal and metallic resistance and capacitance can be measured. This allows
identification of leakage resistance, line capacitance and telephones.
1.3.7 Common Analog Block
The Common Analog block contains the PLL and voltage reference for the octal SLAC.
1.3.8 Digital Front End
The Digital Front End block contains the interpolators for the DACs, the decimators for the ADC and the metering
generation and cancellation logic.
1.3.9 Analog Front End
The Analog Front End block contains the ADCs and DACs necessary to interface to the SLIC plus the associated
buffers.
1.3.10 SLIC-SLAC Interface
The SLIC is a voltage feed device which drives line voltage and measures line current. Feedback inside the SLAC
is used to generate the appropriate input impedances and current limits.
There are three analog voltage control signals from the SLAC to the SLIC, the DC and low-frequency A-lead control
voltage (DCA), the DC and low-frequency B-lead control voltage (DCB), and the combined voice and metering
differential control voltage (RCVP, RCVN).
There are three analog current sense signals from the SLIC to the SLAC, IAB current (IMT); IA current (IA), and IB
current (IB). The voice signal is generated from the measured IAB current. There is also a connection to a metering
cancellation DAC to cancel the metering signal from the voice path to prevent metering overload in the transmit
path.
There are sense resistors connected directly from the A (Tip) and B (Ring) leads to the SLAC to measure foreign
voltages.
There are also sense resistors connected directly from the ringing feed resistor to the SLAC to measure ringing
voltages for external ringing applications.
Finally, there is a digital control bus called the P-bus to control the operating modes of the SLIC.
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2.0 Hardware Design Interfaces
This section discusses the supported hardware interfaces between the NGCC devices and between the NGCC
devices and an external processor.
2.1 Host Bus Interface - VCP Device
The Host Bus Interface (HBI) on the VCP device provides a means for exchanging control, configuration, and
status information with an external host processor. This interface is implemented through a combination of
hardware and firmware. The design is layered as shown in Figure 3. Hardware provides a generic means for
transporting data between the host and internal memory. The interpretation of the data is provided by firmware
running on the VCP device. This layered architecture allows the definition of the application level interface to
change by modifying the firmware.
The hardware interface of the HBI is the General Purpose Parallel Interface (GPI) or the Serial Peripheral Interface
(SPI). Options are selected via the configuration pins, refer to Table 1.
Figure 3 - Host Bus Interface Layers
2.1.1 General Purpose Parallel Interface - VCP Device
The GPI has several configuration options and has been architected to connect gluelessly to a variety of external
processors. The GPI interface uses a combination of write, read, data, address, and wait strobes; thus, a dedicated
clock is not needed to synchronize the transfers.
The GPI can be configured for either 8-bit or 16-bit data bus transfers. Commands and data can be transferred
across the parallel interface using either separate read and write strobes or using a combined read/write strobe and
a data strobe.
A wait strobe can be used to indicate to the external processor that the interface is available for a transfer. When
the wait strobe goes active, the interface is busy. The transfer will complete after the wait signal deasserts. The wait
strobe pin polarity is programmable and defaults to tri-state. Note: an external pull-up or pull-down (depending on
the programmed active state) is required.
CONF2 - CONF0Host Interface Parallel Data Width Parallel Read/Write Strobes
000 Parallel 8 Combined
001 Parallel 8 Separate
010 Parallel 16 Combined
011 Parallel 16 Separate
100 Serial NA NA
Table 1 - Configuration Assignments (CONF2 - CONF0)
Provides the application programmer’s interface. Defines
the meaning of payload data passed over the interface.
Defines the pins, signal timing and electrical characteristics
of the interface.
Moves 16-bit data words between the physical layer and
internal memory.
Firmware
Hardware
Transport Layer
Physical Layer
Application Layer
SPIGPI
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The external interface connection diagrams for the four different GPI configurations are shown in Figure 4 through
Figure 7.
Figure 4 - GPI - 8-bit Parallel Control, Combined Read/Write and Data Strobe
Figure 5 - GPI - 8-bit Parallel Control, Separate Read and Write Strobes
PD0
Le79124 or
Le79128 or
Le79234
VCP PD1
PD2
PD3
PD4
PD5
PD6
PD7
PADDR
PCS
CONF0
CONF1
CONF2
DVDD
DVSS
+3.3 VVDD18+1.8 V
PWAIT
PLL_VSS
PLL_VDD
R
UP
+3.3 V
- Connection of processor to the VCP PWAIT pin is optional.
Note:
PDS
PRD/WR
Bus
Address
Chip Select
Data Strobe
Read/Write
Wait
Host
Processor
PD0
Le79124 or
Le79128 or
Le79234
VCP PD1
PD2
PD3
PD4
PD5
PD6
PD7
PADDR
PCS
CONF0
CONF1
CONF2
DVDD
DVSS
+3.3 VVDD18+1.8 V
PWAIT
PLL_VSS
PLL_VDD
RUP
+3.3 V
- Connection of processor to the VCP PWAIT pin is optional.
Note:
PRD
PWR
Bus
Address
Chip Select
Read
Write
Wait
Host
Processor
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Figure 6 - GPI - 16-bit Parallel Control, Combined Read/Write and Data Strobe
Figure 7 - GPI - 16-bit Parallel Control, Separate Read and Write Strobes
PD0
Le79124 or
Le79128 or
Le79234
VCP PD1
PD2
PD3
PD4
PD5
PD6
PD7
PADDR
PCS
CONF0
CONF1
CONF2
DVDD
DVSS
+3.3 VVDD18+1.8 V
PWAIT
PLL_VSS
PLL_VDD
R
UP
+3.3 V
- Connection of processor to the VCP PWAIT pin is optional.
Note:
PDS
PRD/WR
Bus
Address
Chip Select
Data Strobe
Read/Write
Wait
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
Host
Processor
PD0
Le79124 or
Le79128 or
Le79234
VCP PD1
PD2
PD3
PD4
PD5
PD6
PD7
PADDR
PCS
CONF0
CONF1
CONF2
DVDD
DVSS
+3.3 VVDD18+1.8 V
PWAIT
PLL_VSS
PLL_VDD
R
UP
+3.3 V
- Connection of processor to the VCP PWAIT pin is optional.
Note:
PRD
PWR
Bus
Address
Chip Select
Read
Write
Wait
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
Host
Processor
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2.1.2 Serial Peripheral Interface - VCP Device
The SPI is an alternate physical interface that can be used by the external host to communicate with the VCP
device. The SPI interface is compatible with the SPI interface used by general DSP devices allowing the VCP to be
interfaced without glue logic. The SPI has the same logical view as the GPI so the host can issue the same
commands or data to the VCP regardless of the physical interface.
The most important factor with regards to the ability to use the SPI interface is not the clock speed or
number of lines, but the host architecture. Required is a queued SPI with task resume capability and the
host application broken into enough threads to allow for the SPI to not bottleneck or stall the network
processor. Microsemi strongly recommends the GPI 16-bit architecture. If the SPI architecture is chosen, it
is the responsibility of the software designer to correctly architect the host firmware.
A 4-wire serial interface is shown in Figure 8. If the host processor does not provide a slave select and only one
VCP is used, simply tie VCP SS to ground.
Figure 8 - SPI - 4-wire
2.1.3 HBI Timing Requirements - VCP Device
Timing requirements and command and data structures for the VCP parallel and serial interfaces are detailed in the
Le79124, Le79128, and Le79234 VCP data sheets.
2.2 Debug Interfaces - VCP Device
Microsemi recommends that footprints for two connectors be provided for in the PCB layout. Having access to the
VCP HBI/PCM interface and Debug port can help to facilitate initial line card start-up.
2.2.1 HBI/PCM Interface Header
The HBI/PCM interface header is a 38-position matched impedance socket (Mictor) mounted on the line card.
When properly configured, the header allows the line card to be controlled by the Microsemi Le71HP0300 or
Le71HP0400 platform instead of the user’s control interface. The header will receive a cable that interfaces to the
platform’s DIN connector.
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The PCB should be laid out to accept a Tyco Electronics 38-position receptacle, part number 2-5767004-2, or
equivalent. On production line cards, this socket does not need to be populated. Figure 9 defines the pin-out of the
socket. Note that in addition to the 38 signal positions, the socket provides 5 ground connections.
When this interface is used, it needs to be isolated from the user’s control interface. One way to provision for this is
to use series termination resistors on each PCM and HBI signal and then to simply remove them if the debug
interface is to be used. An example of series termination placement is shown in Figure 10. Signals driven from the
Host Processor or Network Interface have series termination resistors placed near their respective drivers. Signals
driven from the VCP have series termination resistors placed near the VCP, but placed on the other side of the
mictor socket so that the mictor socket can be fully isolated during a debug implementation.
Figure 9 - Mictor Socket Pin-out
Figure 10 - Series Termination Resistor Placement
MICTOR
PADDR
PCS
GND
PWAIT
PWR
PRD
PD13
PD14
PD15
2
4
6
8
10
12
PD11
PD12 14
16
18
PD10
PD7
PD8
20
PD5
PD6
PD4
22
24
26
28
30
PD9
PD3
PD1
PD2
PD0
34
36
38
32
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
33
35
37
31
39 40 41 42 43
RST
INT
PCLKA
FSA
DRA (VCP)
DXA (VCP)
PCLKB
FSB
DRB (VCP)
DXB (VCP)
MPCLK
MFS
MDR (VCP)
MDX (VCP)
PD0 - PD15
Le79124 or
Le79128 or
Le79234
VCP
PWAIT
DXx, MDX
Host
Processor
Network
Interface
PCLKx, FSx,
DRx, MDR
RST, INT, PRD,
PADDR, PWR, PCS
Mictor
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2.2.2 Debug Port
The Debug port on the VCP device consists of the TCK, TMS, TDI, TDO, and TRST pins. This port is for Microsemi
debug use only. If debug of VCP operation becomes necessary, Microsemi may require access to this port.
Two Debug port access methods are presented.
The board can be laid out with a population option debug header and with population option pull-up and pull-down
resistors. This interface is detailed in Figure 11. The 14-pin header pins should be spaced 2.54 mm (100 mils) row
to row and 2.54 mm (100 mils) column to column.
An alternate approach is to simply bring TCK, TMS, TDI, TDO, and TRST pins out to test points with TRST tied to
digital ground through a 1 KΩ resistor. This will allow easy access if it becomes necessary to jumper to the Debug
port. Holding TRST low ensures that the Debug port is kept in reset during power supply bring-up. This resistor (R3
in Figure 11 and RTRST in Figure 49 and Figure 50) is recommended for all new designs.
Figure 11 - VCP Debug Port - Optional Header Interface
2.3 Host Bus Interface - SLAC Device
Like the VCP device, the Host Bus Interface for the SLAC device provides a means for exchanging control,
configuration and status information with an external processor. This interface is implemented through a
combination of hardware and firmware. The design is layered as shown in Figure 12. Hardware provides a generic
means for transporting data between the host and internal memory. The interpretation of the data is provided by
firmware running on the internal DSP. This layered architecture allows the definition of the application level interface
to change by modifying the firmware.
The SLAC device supports a SPI hardware interface. The SPI (also referred to as a Microprocessor Peripheral
Interface (MPI)) is compatible with the SPI used by general DSP devices, so interfacing with the SLAC device can
be accomplished without glue logic.
The SPI is a common 4-wire synchronous serial interface. The HBI includes a slave SPI implementation, which
means the serial clock is supplied by an external master. This slave SPI supports both 8-bit or 16-bit masters and
supports masters that independently control chip select.
1 2
34
5 6
78
910
11 12
13 14
R1
10K
R3
1K
R2
33
R4
0
R5
0
+3.3 V
TDI
TDO
TCK
TMS
TRST
Le79124 or
Le79128 or
Le79234
VCP
Debug
Header
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Figure 12 - Host Bus Interface Layers
2.3.1 SPI on SLAC Device
This section discusses direct connection of the SLAC device SPI to an external host processor, when no VCP
device is used. Timing requirements and command and data structures for the SLAC SPI are detailed here.
When using the SPI port on the SLAC device to communicate with an external host processor, the SLAC device is
the SPI slave and the external host is the SPI master. SPI signals are wired to the SLAC pins as shown in Table 2.
The SLAC devices sample the input signal DIN on the rising edge of the clock and change the output signal DOUT
on the falling edge of the clock.
Figure 13 shows the SPI interface system with a 4-wire SPI master. TI DSP devices and Motorola 68HC12 devices
have a 4-wire SPI master. For example, the TI TMS320F28x chips can set the chip as the master (SPICTL[2]=1), 8-
bit (SPICCR[3:0]=7) transfer with clock polarity (SPICCR[6]=1 falling), clock phase (CPICTL[3]=0 no delay) or with
SPICCR[6]=0 (rising), CPICTL[3]=1 (delay) to connect to the SLAC device.
Figure 14 shows the SPI interface system with an alternate SPI master. Most Motorola DSP/controllers, except
68HC12 and ADI DSP, have 3-wire SPI masters. For example, Motorola 68HC05Cx SPCR register can set the
Clock Phase (CPHA=0) with the clock polarity (CPOL=0) or CPHA=1 with CPOL=1 to interface with the SLAC
device. One of the GPIO pins is needed to drive the CS pin of the SLAC device. As the SLAC device supports
command framing on the CS pin, the GPIO pin of the master connecting to the CS pin of the slave is required, as
shown in Figure 14.
Signal Name (Pin Name) Type Description
SCK (DCLK) I SPI clock
MOSI (DIN) I SPI slave input/master output
MISO (DOUT) O SPI slave output/master input
SS (CS) I SPI Slave select low
Table 2 - SPI-SLAC Interconnect
Transport Layer
Physical Layer
Application Layer
Provides the application programmer’s interface. Defines
the meaning of payload data passed over the interface.
Defines the pins, signal timing and electrical characteristics
of the interface.
Moves 16-bit data words between the physical layer and
internal memory.
SPI
Firmware
Hardware
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Figure 13 - 4-wire Master-Slave Connections
Figure 14 - Alternate Master-Slave Connections
2.3.2 SLAC SPI Timing
In order to connect to different SPI masters and share the same logic view with the VCP GPI, the SPI slave of the
SLAC device has the following designs:
• Separate DIN and DOUT pins.
• No daisy chain support.
• No read latency: no latency between the read command word and the first data word.
• CS pin supports byte/word framing, and command framing mode, as shown in Figure 15. The SPI slave
state machine will reset if CS returns to High when the number of active SCK clock pulses is not equal to 8
or 16. If there is no clock, CS has to be Low for more than 125 ns (depending on the internal clock) to be
recognized to reset the SPI slave state machine. In command framing mode, the transition of CS to High
means the command has ended. This event resets the SPI slave state machine, and the next falling edge of
CS starts a new command.
Figure 15 shows three kinds of framing modes based on the behavior of SS . In byte/word framing mode, SS is Low
for 8/16 SCK clocks. For a two-word command, SS needs to toggle 4/2 times to complete the command transfer. In
command framing mode, SS is Low for the whole duration of the command transfer. When the command is
finished, SS will go back to High. If SS Low lasts shorter than the expected command length, the command is
aborted and the SPI slave state machine resets. However if the user pulls SS Low longer than the expected
command length, the extra words will start a new command sequence. In both byte/word framing mode and
command framing mode, SCK can be free-running or absent when SS is inactive High.
SPI
Slave
SPI
SCK
MOSI
MISO
SS
Master
NGCC SLAC device(s)
CS
MOSI
MISO
SCK
DCLK
DOUT
DIN
SS
SPI
Slave
SPI
SCK
DIN
DOUT
Master
NGCC SLAC device(s)
CS
MOSI
MISO
SCK
GPIO
MOSI
MISO
SCK
SS
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Every time SS returns to High and the number of active SCK clocks is not equal to 8 or 16, the SPI slave state
machine will reset. The next SS Low starts a new command sequence. In command framing mode, the transition
back to High means the end of the command. If SS Low lasts less than 16 SCK clock cycles, no command byte is
processed. If SS Low lasts more than 16 clock cycles, each 16-clock cycles triggers the SPI slave to process the
word until SS returns back to High. The SPI slave will not reset state machine when SS Low lasts exactly 8 or 16
SCK clock cycles to support byte/word framing mode. In byte/word framing mode, the user has to be aware of the
command length, as there is no indication of command boundary.
Command framing is the recommended mode of operation because this mode provides state machine
synchronization of when the command word is expected.
Figure 15 - SS Framing Modes
cmd_wd byte hi
SCK
SI/SO
Byte framing mode
SS
SCK
SI/SO
Command framing mode
SCK
or
SCK
or
cmd_wd byte lo data_wd byte hi data_wd byte low
SS
SCK
SCK
or
command word
SI/SO
Word framing mode
data word
command word data word
SS
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The timing requirements for read and write accesses are shown in the following timing diagrams. The single data
word read and write command is shown in Figure 16 and Figure 17.
Figure 16 - One Data Word Write in Byte Framing Mode
Figure 17 - One Data Word Read in Word Framing Mode
Note 1: SCK may be stopped in the High or Low state indefinitely without loss of information. When SS is at Low state, every 16 SCK
cycles the 16-bit received will be interpreted by the SPI interface logic.
Note 2: The first data bit is enabled on the falling edge of SS or on the falling edge of SCK, whichever occurs last.
Note 3: The SPI slave requires 61ns SS Off time just to make the transition of SS synchronized with SCK clock. In the command
framing mode, there is no SS Off time between each 16-bit command/data and SS is held low until the end of command.
Note 4: If SS is not held low for 16 or 8 SCK cycles exactly, the SPI slave will reset. During byte or word framing mode, SS is held low
for 8 or 16 SCK cycles. During command framing mode, SS is held low for the whole duration of the command. Besides,
multiple commands can be transferred with SS low for the whole duration of the multiple commands. The rising edge of the
SS indicates the end of the command sequence and resets the SPI slave.
cmd_wd[15:8]
SS
SCK
SI
SCK
or
cmd_wd[7:0] data_wd[15:8] data_wd[7:0]
SO
SS
SCK
SCK
or
command word
data word
SI
. . . .
SO
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2.4 VCP to SLAC Control Interface
In addition to the GPI functional block, the VCP devices provide SPI ports which serve as the control interface
between the VCP device and the SLAC devices. The Le79234 VCP device provides one SPI port and the Le79124
and Le79128 VCP devices provide two SPI ports (SPI1 and SPI2). The SPI interfaces are bussed to the SLAC MPI
interface.
The Le79234 VCP can support up to 32 POTS channels, which is 4 octal SLAC devices. The SPI connections
consist of VCP SPI port 1 controlling all 32 channels. VCP GPIO pins are used to control the SLAC chip select and
receive SLAC interrupts. A Le79234 VCP to SLAC interface for 32 channels is presented in Figure 18.
The Le79124 VCP can support up to 72 POTS channels, which is 9 octal SLAC devices. The SPI connections
consist of VCP SPI port 1 controlling the first group of 32 channels and VCP SPI port 2 controlling the second group
of up to 40 channels. VCP GPIO pins are used to control the SLAC chip select and receive SLAC interrupts. A
Le79124 VCP to SLAC interface for 64 channels is presented in Figure 19; a Le79124 VCP to SLAC interface for
72 channels is presented in Figure 20.
The Le79128 VCP can support up to 128 POTS channels, which is 16 octal SLAC devices. The SPI connections
consist of VCP SPI port 1 controlling the first group of 64 channels and VCP SPI port 2 controlling the second group
of up to 64 channels. VCP GPIO pins are used to control the SLAC chip select and receive SLAC interrupts. A
Le79128 VCP to SLAC interface for 128 channels is presented in Figure 21.
Signal integrity for these interfaces is presented in Section 2.4.1.
Figure 18 - Le79234 VCP to SLAC Interface - 32 Channel NGCC Line Card
GPIO0
NGSLAC
NGSLAC
Le79234 VCP
GPIO16
Note:
SPI1_MOSI
SPI1_MISO
SPI1_CLK
NGSLAC
NGSLAC
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
CS0
INT0
U1
U2
U3
U4
- For signal integrity, provide interface bus termination and buering accordingly.
GPIO1
GPIO17
GPIO2
GPIO18
GPIO3
GPIO19
CS1
INT1
CS2
INT2
CS3
INT3
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Figure 19 - Le79124 VCP to SLAC Interface - 64 Channel NGCC Line Card
GPIO0
Le79124 VCP
GPIO16
Notes:
SPI1_MOSI
SPI1_MISO
SPI1_CLK
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
CS0
INT0
U1
U2
U3
U4
U5
U6
U7
U8
- For signal integrity, provide interface bus termination and buering accordingly.
GPIO1
GPIO17
GPIO2
GPIO18
GPIO3
GPIO19
GPIO8
GPIO24
GPIO9
GPIO25
GPIO10
GPIO26
GPIO11
GPIO27
CS1
INT1
CS2
INT2
CS3
INT3
CS8
INT8
CS9
INT9
CS10
INT10
CS11
INT11
SPI2_MOSI
SPI2_MISO
SPI2_CLK
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
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Figure 20 - Le79124 VCP to SLAC Interface - 72 Channel NGCC Line Card
GPIO0
NGSLAC
Le79124 VCP
GPIO16
SPI1_MOSI
SPI1_MISO
SPI1_CLK
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
CS0
INT0
U1
U2
U3
U4
U5
U6
U7
U8
GPIO1
GPIO17
GPIO2
GPIO18
GPIO3
GPIO19
GPIO8
GPIO24
GPIO9
GPIO25
GPIO10
GPIO26
GPIO11
GPIO27
CS1
INT1
CS2
INT2
CS3
INT3
CS8
INT8
CS9
INT9
CS10
INT10
CS11
INT11
SPI2_MOSI
SPI2_MISO
SPI2_CLK
Notes:
- For signal integrity, provide interface bus termination and buering accordingly.
DIN
INT
DCLK
DOUT
CS
U9
GPIO12
GPIO28
CS12
INT12
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
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Figure 21 - Le79128 VCP to SLAC Interface - 128 Channel NGCC Line Card
GPIO0
Le79128 VCP
GPIO16
Notes:
SPI1_MOSI
SPI1_MISO
SPI1_CLK
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
CS0
INT0
U1
U2
U3
U4
U5
U6
U7
U8
- For signal integrity, provide interface bus termination and buering accordingly.
GPIO1
GPIO17
GPIO2
GPIO18
GPIO3
GPIO19
GPIO4
GPIO20
GPIO5
GPIO21
GPIO6
GPIO22
GPIO7
GPIO23
CS1
INT1
CS2
INT2
CS3
INT3
CS4
INT4
CS5
INT5
CS6
INT6
CS7
INT7
SPI2_MISO
NGSLAC
SPI2_MOSI
SPI2_CLK
GPIO8
GPIO24
GPIO9
GPIO25
GPIO10
GPIO26
GPIO11
GPIO27
GPIO12
GPIO28
GPIO13
GPIO29
GPIO14
GPIO30
GPIO15
GPIO31
CS8
INT8
CS9
INT9
CS10
INT10
CS11
INT11
CS12
INT12
CS13
INT13
CS14
INT14
CS15
INT15
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
U9
NGSLAC
U10
NGSLAC
U11
NGSLAC
U12
NGSLAC
U13
NGSLAC
U14
NGSLAC
U15
NGSLAC
U16
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
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2.4.1 VCP to SLAC Interface Signal Integrity
Some measures are necessary to maintain signal integrity of the VCP to SLAC interface. The interface will operate
at frequencies about 8 MHz. Rise and fall times at this frequency along with possible long trace lengths due to the
bussed DCLK, DIN, and DOUT signals, warrants some form of signal integrity conditioning.
One approach is to use an FPGA to buffer all the interface signals. With an FPGA implementation, ensure that the
propagation delays through the FPGA do not violate the data sheet timing specifications.
Another approach is to provide special conditioning to DCLK. SLAC data clock inputs are edge triggered, so fast
clock rise and fall transitions need to be clean and free of reflections. Using a clock driver for the DCLK fanout to the
SLAC devices will ensure clean transitions. Use a series termination resistor at the output of each clock driver.
If traces are kept as short as possible, a simple solution is to use series termination for all signals as shown in
Figure 22 for the Le79234 VCP device, Figure 23 for the Le79124 VCP device, and Figure 24 for the Le79128 VCP
device. Place the series termination resistors close to the respective VCP device or SLAC device as shown.
Whatever method of signal integrity is chosen, the design should be validated by running a signal integrity
simulation analysis. IBIS models are available for the NGCC SLAC and VCP components.
Figure 22 - Le79234 VCP to SLAC 32-Channel Interface - Signal Integrity
GPIO0
Le79234 VCP
GPIO16
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
U1
U2
U3
U4
SPI1_MOSI
SPI1_MISO
SPI1_CLK
GPIO1
GPIO2
GPIO3
All resistors are 39 ohms, 10%, 1/16 W
or equivalent
GPIO17
GPIO18
GPIO19
INT series termination resistors are optional.
NGSLAC
NGSLAC
NGSLAC
NGSLAC
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Figure 23 - Le79124 VCP to SLAC 72-Channel Interface - Signal Integrity
GPIO0
Le79124 VCP
GPIO16
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
GPIO8
GPIO24
U1
U2
U3
U4
U5
U6
U7
U8
U9
SPI1_MOSI
SPI1_MISO
SPI1_CLK
SPI2_MOSI
SPI2_MISO
SPI2_CLK
GPIO1
GPIO2
GPIO3
GPIO9
GPIO10
GPIO11
GPIO12
All resistors are 39 ohms, 10%, 1/16 W
or equivalent
GPIO17
GPIO18
GPIO19
GPIO25
GPIO26
GPIO27
GPIO28
INT series termination resistors are optional.
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
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Figure 24 - Le79128 VCP to SLAC 128-Channel Interface - Signal Integrity
GPIO0
Le79128 VCP
GPIO16
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
DIN
INT
DCLK
DOUT
CS
GPIO8
GPIO24
U1
U2
U3
U8
U9
U10
U11
U16
SPI1_MOSI
SPI1_MISO
SPI1_CLK
SPI2_MOSI
SPI2_MISO
SPI2_CLK
GPIO1
GPIO2
GPIO7
GPIO9
GPIO10
GPIO15
All resistors are 51 ohms, 10%, 1/16 W
or equivalent
GPIO17
GPIO18
GPIO23
GPIO25
GPIO26
GPIO31
INT series termination resistors are optional.
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
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2.4.2 Hardware Reset
The VCP and SLAC devices require either a power up hardware reset or a hardware reset controlled by the host.
Figure 26 shows a reset configuration where the host controls hardware reset of the VCP and SLAC devices. An
advantage of this approach is the host can force a system reset at will. For this configuration, the host must hold
hardware reset low until it completes its initial boot sequence.
For external ringing applications a capacitor to ground is recommended at the device reset pins. Figure illustrates
hardware reset for an external ringing application.
Figure 25 - Hardware Reset
Figure 26 - Hardware Reset for External Ringing Applications
Host
Processor
Le79234
or
Le79124
or
Le79128
RST
Le79238
RST
Le79238
RST
Le79238
RST Reset
Host
Processor
ZL79258
RST
ZL79258
RST
ZL79258
RST Reset
C
RST
C
RST
C
RST
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2.5 PCM Interface
The PCM bus connects between the SLAC devices and the Network Interface, and the VCP device if used.
The PCM port of the SLAC and VCP devices interface to the external transmit and receive PCM highway(s). Dual
PCM highways are supported.
Choice of PCM clock frequency and number of highways is dependent upon the number of channels and timeslot
usage. A normal voice channel only requires a single 8-bit time slot but wideband mode (if used) requires four 8-bit
time slots (two sets of 16-bit time slots). Testing requires two consecutive 8-bit time slots and the 15 kHz noise test
requires 8 consecutive transmit channels to execute. An 8.192 MHz PCM clock provides 128 slots. For a 72
channel architecture if all 72 channels are assigned to individual 8-bit time slots, only 56 time slots are available for
testing. So simply allocating two consecutive time slots to each channel is not possible with only one PCM highway.
Time slots are assigned on a per line basis via VP_OPTION_ID_TIMESLOT and the PCM highway is assigned on
a per line basis via VP_OPTION_ID_PCM_HWY. Line test works in linear mode so two time slots per channel are
required. For line test the VCP keeps an image of the time slot assignments, so there is no need to do a
reassignment. But the host must make sure that the adjacent timeslot is not assigned as the VCP will not keep track
of that. For instance, if there is a voice channel assigned to time slot 5, when a test is initiated on that same
channel, the VCP will know the channel is on time slot 5, but the VCP will not check to see if time slot 6 is available
− the VCP assumes this time slot is available.
Taking into account the device level restrictions listed below, an alternative approach to time slot assignment during
testing is to put the voice time slots adjacent to each other and reserve a block of 8 time slots for testing. And if the
15 kHz noise test is to be used, reserve an additional block of 16 time slots.
A system operating with a dynamic time slot assignment architecture shall allocate a time slot to a channel before
executing a line test on it in case the test function needs to perform a data transfer over the PCM bus.
Note these device level restrictions:
• Up to 4 lines in line testing simultaneously running per VCP device, of these, only 2 can be the 15 kHz noise
test.
• With VCP device use, up to 2 lines in line testing simultaneously running per SLAC device, of these, only 1
can be the 15 kHz noise test. Without VCP device use, one line test running per SLAC device at a time.
2.5.1 PCM Interface - SLAC Device
The SLAC PCM port can transmit/receive 8-bit compressed (A-law/µ-law) data or 16-bit linear data.
An 8 kHz frame sync signal indicating the beginning of a transmit/receive frame shall be supplied by the system and
all time slots shall be referenced to it.
The SLAC devices will accept PCM clock frequencies (as defined in the SLAC data sheets) up to 8.192 MHz,
synchronous to the frame sync signal. Thereby supporting up to 128 voice channels of 8-bits per highway in one
frame of data.
Each time slot can carry one A-law or µ-law PCM voice channel. Two time slots are required to carry 16-bit linear
data. The time slots are user programmable but are common for both highway channels. The transmit data can be
sent out on highway A (DXA) or highway B (DXB) or both highways. This is programmable on a per channel basis.
When using the wideband transmission mode, two 16-bit linear samples are transmitted within each 8-kHz frame
using two time slots. The API only allows allocating one time slot per channel and it will be used by the first byte of
the first data word. The second byte of the first data word uses the adjacent time slot. The two bytes of the second
data word will use a mirror time slot located exactly a half-frame away from the assigned time slot. Therefore, when
using the wideband mode, the assigned time slot must be located within the first half of the 8-kHz frame.
Data can be transmitted on the positive or negative edge of PCLK. Receive data is always evaluated on the
negative edge of PCLK.
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To avoid timing and clock skew problems, the PCM port has a clock slot feature that allows the transmit and receive
data to be independently offset from the zero time slot defined in relation to the frame sync signal applied. The clock
slot permits 0-7 PCLK cycles of delay from the position defined by the applied frame synchronization signal.
2.5.1.1 PCM Transmit Interface - SLAC Device
The PCM transmit interface controls the transmission of data onto the PCM highway through the output port
selection circuitry and the time and clock slot control block. The time slot control signal (TSCx ) goes low whenever
PCM data is transmitted on the DX pin. These signals can be used for arbitration when there are multiple devices
connected to the PCM bus. The data can be transmitted on either edge of PCLK. The clock edge at which the data
is transmitted is selected by the XE bit in the Transmit Receive Clock Slot Register. The data is transmitted with the
most significant bit first.
The Frame Sync (FS) pulse identifies time slot 0 of the transmit frame and all time slots are referenced to it.
2.5.1.2 PCM Receive Interface - SLAC Device
The PCM Receive interface logic controls the reception of the data bytes from the PCM highway. Each time slot is
associated with one 8-bit data byte. The data is received with the most significant bit first. The received data coming
on the DR pin is latched at the falling edge of PCLK.
2.5.1.3 PCM Timing
Figure 27 and Figure 28 illustrate the timing on the PCM highway for 8-bit and 16-bit transfers. Here is a key for the
timing diagrams, these parameters are selected in the Device Profile.
• XE = 0, Transmit changes on negative edge of PCLK
• XE = 1, Transmit changes on positive edge of PCLK
• RCS is Receive PCM Clock Slot delay number from 0 to 7
SLAC Pin
Name Type Reset Description
DXA Output High
Impedance
Primary downstream serial data output
DXB Output High
Impedance
Secondary downstream serial data output
TSCA Output High
Impedance
Primary timeslot control signal (active low - open drain)
TSCB Output High
Impedance
Secondary timeslot control signal (active low - open drain)
DRA Input Primary upstream serial data input
DRB Input Secondary upstream serial data input
PCLK Input PCM Interface clock
FS Input 8 kHz Frame sync
Table 3 - SLAC PCM Interface Pins
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• TCS is Transmit PCM Clock Slot delay number from 0 to 7
2.5.2 PCM Interface - VCP Device
The VCP device connects to the SLAC PCM port. It uses the PCM highway for testing. The VCP PCM ports are
described in Section 2.5.3.
Figure 27 - PCM Highway 8-bit Transfers
CASE 1 : DEFAULT: XE = RCS = TCS = 0 (8-bit TRANSFERS)
PCLK
FS
DR
DX
TSC
RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
CASE 2 : XE = 1 RCS = 2 TCS = 4 (8-bit TRANSFERS)
PCLK
RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
TX7 TX6 TX5 TX4
TX3
TX2
FS
DR
DX
TSC
Timeslot 0
Timeslot 0
NGCC
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Figure 28 - PCM Highway 16-bit Transfers
2.5.3 PCM Hardware Interfaces
The PCM interface can be used in a variety of ways. To facilitate connection of this interface, a number of supported
hardware interfaces are presented in the following figures. For all applications, unused PCM port pins are tied to
ground to eliminate the potential of excess current draw and noise due to floating nodes.
PCM wiring with use of the SLAC device only is shown in Figure 29 and Figure 30.
Figure 29 illustrates use of the SLAC Highway A port and Figure 30 illustrates use of both Highway A and Highway
B ports. The SLAC requires PCLK and FS as inputs. System transmit (SYS_DX) is wired to SLAC data receive port
(DRA or DRB). The SLAC data transmit port (DXA or DXB) is wired to the system receive (SYS_DR).
The remaining hardware interfaces all use the VCP device.
Two PCM blocks that reside on the VCP device are highlighted. There is a Slave PCM Highway A/Redundant block
comprised of the PCLKA, FSA, DXA, DRA, TSCXA , TSCRA, PCLKB, FSB, DXB, DRB, TSCXB, and TSCRB pins,
and a block used as the Slave PCM Highway B comprised of the MPCLK, MFS, MDX, and MDR pins. The Slave
PCM Highway A/Redundant block requires PCLKA or PCLKB as inputs. The Slave PCM Highway B requires
MPCLK as an input. PCLKA and PCLKB are monitored for clock faults.
The Slave PCM Highway A/Redundant block provides backplane driver tri-state control outputs TSCXA and
TSCXB when DXA or DXB are active respectively. These are generally not used and do not appear in any of the
following hardware drawings. The Slave PCM Highway B block does not have a tri-state control output.
The first VCP hardware interface uses a single PCM highway. This architecture is presented for 32-channel, 64-
channel, and 72-channel applications. The applications will support any valid PCM clock frequency.
A 32-channel PCM interface is shown in Figure 31 using the Le79234 VCP device. Four octal SLAC devices share
the same PCM highway. VCP Slave PCM Highway A is used and it services voice and data for all channels. The
PCM highway runs off of SYS_PCLK and SYS_FS from the backplane.
PCLK
FS
DR
CASE 1 : XE = RCS = TCS = 0 (16-BIT TRANSFERS)
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
DX
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
TSC timeslot0 timeslot1
CASE 2 : XE = 1 RCS = TCS = 0 (16-BIT TRANSFERS)
FS
DR
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
DX
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
TSC timeslot0 timeslot1
PCLK
NGCC
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A 64-channel PCM interface is shown in Figure 32. Eight octal SLAC devices share the same PCM highway. VCP
Slave PCM Highway A is used and it services voice and data for all channels. The PCM highway runs off of
SYS_PCLK and SYS_FS from the backplane. For a 72-channel design, use a ninth SLAC device as shown in blue
in Figure 32.
Figure 33 illustrates a Dual PCM highway option. The VCP Slave PCM Highway A services voice and data for the
first group of 32 channels. The VCP Slave PCM Highway B services voice and data for the second group of 40
channels. Slave PCM Highway A is wired to SLAC PCM port A, Slave PCM Highway B is wired to SLAC PCM port
B (that is, DRB and DXB of the SLAC). PCM Highway 1 runs off of SYS_PCLK1/SYS_FS1 and PCM Highway 2
runs off of SYS_PCLK2/SYS_FS2 from the backplane. PCLKB to MPCLK and FSB to MFS connections allow clock
failure detection to monitor the Slave PCM Highway B. Tie PCLKB and FSB to ground if these connections are not
used.
Figure 34 illustrates an alternative wiring for two PCM highways. Here both highways use a common PCLK and FS
signal.
Figure 35 illustrates a separate Voice PCM highway and Test PCM highway option. The VCP Slave PCM Highway
A services voice and data for all 72 channels. Slave PCM Highway A is wired to SLAC PCM port A on all SLAC
devices. The VCP Slave PCM Highway B services all 72 channels but is dedicated to line testing. The Slave PCM
Highway B is wired to SLAC port B (that is, DRB and DXB) on all SLAC devices. VCP MPCLK and MFS pins
connect to SYS_PCLK and SYS_FS respectively, as the VCP Highway B is a slave to the clocking. The PCM and
Test highways are synchronized and both run off of SYS_PCLK and SYS_FS from the backplane.
Figure 36 illustrates a Dual PCM highway option using the 128-channel Le79128 VCP device. The VCP Slave PCM
Highway A services voice and data for the first group of 64 channels. The VCP Slave PCM Highway B services
voice and data for the second group of 64 channels. Slave PCM Highway A is wired to SLAC PCM port A, Slave
PCM Highway B is wired to SLAC PCM port B (that is, DRB and DXB of the SLAC). PCM Highway 1 runs off of
SYS_PCLK1/SYS_FS1 and PCM Highway 2 runs off of SYS_PCLK2/SYS_FS2 from the backplane. PCLKB to
MPCLK and FSB to MFS connections allow clock failure detection to monitor the Slave PCM Highway B. Tie
PCLKB and FSB to ground if these connections are not used.
Note, even though the Le79124 VCP device is shown in the PCM highway options detailed in Figures 34 – 36, the
Le79234 VCP device could also be used to control up to 32 channels.
NGSLAC
PCLK
FS
DRA
DXA
SYS_PCLK
SYS_FS
SYS_DX
SYS_DR
Network Interface
+3.3 V
10K
RSTZ
RSTZ
RSTZ
RSTZ
DRB
Note: This interface requires measures to ensure signal integrity. If a series termination
resistor is used (RSTZ), select an appropriate value by running a signal integrity simulation.
PCM Bus
(To additional SLAC devices)
NGCC
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Figure 29 - SLAC PCM Interface - Highway A
Figure 30 - SLAC PCM Interface - Highway A & B
NGSLAC
PCLK
FS
DRA
DXA
SYS_PCLK
SYS_FS
SYS_DXA
SYS_DRA
Network Interface
+3.3 V
10K
RSTZ
RSTZ
RSTZ
RSTZ
DRB
Note: This interface requires measures to ensure signal integrity. If a series termination
resistor is used (RSTZ), select an appropriate value by running a signal integrity simulation.
DXB RSTZ
RSTZ SYS_DXB
SYS_DRB
10K
PCM Buses
(To additional SLAC devices)
FSA
PCLKA
NGSLAC
Le79234
VCP
PCLK
FS
DRA
DXA
DXA
DRA
SYS_PCLK
SYS_FS
SYS_DX
SYS_DR
Network Interface
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
+3.3 V
10K
FSB
PCLKB
DXB
DRB
RSTZ
RSTZ
RSTZ
NGSLAC
NGSLAC
NGSLAC
DRB
DRB
DRB
DRB
Note: This interface requires measures to
ensure signal integrity. If a series termination
resistor is used (RSTZ), select an appropriate
value by running a signal integrity simulation.
MPCLK
MDX
MDR
MFS
Slave PCM
Highway A
RSTZ
RSTZ
DVSS
+3.3 V
10K
NGCC
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Figure 31 - VCP-SLAC PCM Interface - 32 Channel NGCC Line Card - Single PCM Highway
Figure 32 - VCP-SLAC PCM Interface - 64 or 72 Channel NGCC Line Card - Single PCM Highway
FSA
PCLKA
NGSLAC
Le79124
VCP
PCLK
FS
DRA
DXA
DXA
DRA
SYS_PCLK
SYS_FS
SYS_DX
SYS_DR
Network Interface
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
+3.3 V
10K
FSB
PCLKB
DXB
DRB
R
STZ
R
STZ
R
STZ
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
Note: This interface requires measures to
ensure signal integrity. If a series termination
resistor is used (R
STZ
), select an appropriate
value by running a signal integrity simulation.
MPCLK
MDX
MDR
MFS
Slave PCM
Highway A
R
STZ
R
STZ
DVSS
PCLK
FS
DRA
DXA
NGSLAC
DRB
Use this SLAC for a 72 channel design.
+3.3 V
10K
NGCC
Design Guide
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Microsemi Corporation Confidential and Proprietary
Figure 33 - VCP-SLAC PCM Interface - 72 Channel NGCC Line Card - Dual PCM Highways
FSA
PCLKA
NGSLAC
NGSLAC
Le79124
PCLK
FS
DRA
DXA
DXA
DRA
SYS_PCLK1
SYS_FS1
SYS_DX1
SYS_DR1
Network Interface
NGSLAC
NGSLAC
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRB
DXB
PCLK
FS
DRB
DXB
PCLK
FS
DRB
DXB
PCLK
FS
DRB
DXB
NGSLAC
NGSLAC
NGSLAC
NGSLAC
+3.3 V
U1
U2
U3
U4
U5
U6
U7
U8
NGSLAC
PCLK
FS
DRB
DXB
U9
DRB
DRB
DRB
DRB
DRA
DRA
DRA
DRA
DRA
MPCLK
MFS
MDX
MDR
Network Interface
SYS_PCLK2
SYS_FS2
SYS_DX2
SYS_DR2
Slave PCM
Highway A
Slave PCM
Highway B
PCM Highway 2
PCM Highway 1 RSTZ
RSTZ
RSTZ
PCLKB
DXB
DRB
FSB
DVSS
RSTZ
Note: This interface requires measures to
ensure signal integrity. If a series termination
resistor is used (R
STZ ), select an appropriate
value by running a signal integrity simulation.
RSTZ
RSTZ
Note: PCLKB to MPCLK and FSB to MFS
connections are optional. Tie PCLKB and
FSB to ground if these connections are not
used.
10K
+3.3 V
10K
+3.3 V
10K
10K
NGCC
Design Guide
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Microsemi Corporation Confidential and Proprietary
Figure 34 - VCP-SLAC PCM Interface - 72 Channel NGCC Line Card - Two PCM Highways with a
Single Clock and Frame Sync
FSA
PCLKA
NGSLAC
NGSLAC
Le79124
PCLK
FS
DRA
DXA
DXA
DRA
SYS_PCLK1
SYS_FS1
SYS_DX1
SYS_DR1
System PCM Interface 1
NGSLAC
NGSLAC
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRB
DXB
PCLK
FS
DRB
DXB
PCLK
FS
DRB
DXB
PCLK
FS
DRB
DXB
NGSLAC
NGSLAC
NGSLAC
NGSLAC
U1
U2
U3
U4
U5
U6
U7
U8
NGSLAC
PCLK
FS
DRB
DXB
U9
DRB
DRB
DRB
DRB
DRA
DRA
DRA
DRA
DRA
MPCLK
MFS
MDX
MDR
System PCM Interface 2
+3.3 V
SYS_DX2
SYS_DR2
PCM Highway 2
PCM Highway 1 RSTZ
RSTZ
PCLKB
DXB
DRB
FSB
DVSS
RSTZ
Note: This interface requires measures to
ensure signal integrity. If a series termination
resistor is used (RSTZ), select an appropriate
value by running a signal integrity simulation.
RSTZ
Slave PCM
Highway A
Slave PCM
Highway B
RSTZ
RSTZ
10K
10K
+3.3 V
10K
10K
NGCC
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Microsemi Corporation Confidential and Proprietary
Figure 35 - VCP-SLAC PCM Interface - 72 Channel NGCC Line Card - Separate Voice and Test
PCM Highways
FSA
PCLKA
NGSLAC
NGSLAC
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
DXA
DRA
SYS_PCLK
SYS_FS
SYS_DX
SYS_DR
U1
U4
+3.3 V
Network Interface
NGSLAC
NGSLAC
U5
U9
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
RSTZ
MDX
MDR
PCM Highway
DRB
DXB
DRB
DXB
DRB
DXB
DRB
DXB
Test
Highway
Slave PCM
Highway A
Le79124
PCLKB
FSB
DXB
DRB
DVSS
MPCLK
MFS
RSTZ
Note: This interface requires measures to
ensure signal integrity. If a series termination
resistor is used (RSTZ), select an appropriate
value by running a signal integrity simulation.
Slave PCM
Highway B
RSTZ
RSTZ
RSTZ
+3.3 V
10K
10K
+3.3 V
10K
10K
NGCC
Design Guide
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Microsemi Corporation Confidential and Proprietary
Figure 36 - VCP-SLAC PCM Interface - 128 Channel NGCC Line Card - Dual PCM Highways
Le79128 VCP
DRA
FSA
DXA
PCLKA
FS
PCLK
DRA
DXA
U1
U2
U3
U4
U5
U6
U7
U8
MDX
NGSLAC
MFS
MPCLK
MDR
FS
PCLK
DRB
DXB
U9
NGSLAC
U10
NGSLAC
U11
NGSLAC
U12
NGSLAC
U13
NGSLAC
U14
NGSLAC
U15
NGSLAC
U16
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
NGSLAC
SYS_PCLK1
SYS_FS1
SYS_DX1
SYS_DR1
Network Interface
+3.3 V
PCM Highway 1
RSTZ
FS
PCLK
DRA
DXA
FS
PCLK
DRA
DXA
FS
PCLK
DRA
DXA
FS
PCLK
DRA
DXA
FS
PCLK
DRA
DXA
FS
PCLK
DRA
DXA
FS
PCLK
DRA
DXA
RSTZ
RSTZ RSTZ
PCM Highway 2
SYS_PCLK2
SYS_FS2
SYS_DX2
SYS_DR2
RSTZ
RSTZ
FS
PCLK
DRB
DXB
FS
PCLK
DRB
DXB
FS
PCLK
DRB
DXB
FS
PCLK
DRB
DXB
FS
PCLK
DRB
DXB
FS
PCLK
DRB
DXB
FS
PCLK
DRB
DXB
Slave PCM
Highway A
Slave PCM
Highway B
DXBDRB
PCLKB
FSB
Note: This interface requires measures
to ensure signal integrity. If a series
termination resistor is used (RSTZ),
select an appropriate value by running
a signal integrity simulation.
Note: PCLKB to MPCLK and FSB to
MFS connections are optional. Tie
PCLKB and FSB to ground if these
connections are not used.
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRA
DRA
DRA
DRA
DRA
DRA
DRA
DRA
10K 10K
+3.3 V
10K
+3.3 V
10K
NGCC
Design Guide
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2.5.3.1 PCM Signal Integrity
Some measures are necessary to maintain signal integrity at the system PCM interface. The system interface
provides PCLK, FS, and DX signals to the SLAC and VCP devices. SLAC and VCP data clock inputs are edge
triggered, so fast clock rise and fall transitions need to be clean and free of reflections.
Using a clock driver for the PCLK and FS fanout to the SLAC devices will ensure clean transitions. With this
method, each SLAC device (or a smaller group of SLAC devices) has its own individual clock or frame sync signal
routed to it. Use a series termination resistor at the output of each clock driver or other appropriate end termination.
Another approach is to use an FPGA to buffer all the PCM signals. If this approach is used, ensure that FPGA
propagation delays do not violate the data sheet timing specifications.
If an FPGA is not used to buffer SLAC DXA, then a single series resistor after the final connection point of all the
SLAC devices, as shown in all the hardware interfaces, may be adequate for this signal.
Whatever method of signal integrity is chosen, the design must be validated by running a signal integrity simulation
analysis. IBIS models are available for the NGCC SLAC and VCP components.
2.6 SLAC-SLIC Interface
The analog interface between the SLAC and SLIC devices (for internal ringing) is shown in Figure 37. Component
values for this and other interfaces are listed in Section 3.0.
2.6.1 RCVP, RCVN
This path provides the receive metallic transmission voltage to the loop, both the receive ac transmission signal and
the metering signal go through this path. The receive differential interface is filtered between the SLAC and SLIC
devices. RCVP
, RCVN, and CM make up the low pass noise filter.
2.6.2 DCA, DCB
This is the DC feed control path to the SLIC. The DC feed control path includes a low pass filter in order to limit
noise on the voiceband and data band. This is made of the C DCA and CDCB capacitors and an internal resistance.
The cut-off frequency of this low pass filter is nominally set to approximately 36 Hz using the defined external
capacitance.
The corner frequency of the dc feed low-pass filter is a function of the internal source resistance feeding the signal
to the external capacitor. A different internal resistor value is selected as necessary in order to provide a different
time constant. The bandwidth of the DC feed path is increased to approximately 145 Hz during ringing, after an on-
hook or an off-hook transition, after the firmware detects that the host has changed the dc feed template, during fast
reversal, and during slow reversal if the line is on-hook.
The internal resistance can also be removed to obtain a very fast response such as to allow generating higher
frequency signals during line testing. This increases the bandwidth to approximately 2 kHz.
2.6.3 IA, IB
A current proportional to the respective A or B lead current is directly connected from the SLIC to the SLAC.
2.6.4 IMT, VIMT, VAC
Metallic loop current proportional to the differential current in the SLIC devices A and B leads is directly coupled
from the SLIC to the SLAC. RIMT converts the current to a voltage for the VIMT SLAC input. C VAC removes the dc
content and the transmit ac transmission signal is applied to the SLAC VAC input.
NGCC
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2.6.5 CANCEL
If metering is used, capacitor C CAN is required. During a metering burst, the SLAC applies a cancellation signal into
the transmit path effectively removing any metering current sense.
2.6.6 SVA, SVB
These pins sense the A and B lead voltages through high impedance resistors. The tolerance of the resistors
determines the accuracy of the integrated testing. A 1%, 200 ppm resistor can be used. For higher accuracy, use a
0.5%, 100 ppm resistor. If PTC protection is used, the sense resistors must be able to withstand high voltages from
fault conditions when the PTC goes into its high impedance state. Select a resistor with an appropriate voltage
rating.
2.6.7 Battery Supplies and Battery Sense
RSPB, RSLB, and RSHB sense the battery voltages. If only one negative battery is used, connect both negative
battery resistors (RSLB and RSHB) to the same supply and wire VBH to VBL as shown in Figure 37. If no positive
supply is used, connect the sense resistor R SPB to ground.
The battery sense pins are current inputs whose voltage is held at VREF.
2.6.8 LD, SEL, and P-Bus
These digital lines which control the SLIC state and switches are all direct connect lines between the SLAC and the
SLIC.
The SLIC P-BUS interface uses a 4 bit parallel bus (SEL, P[2:0]) and eight individual load pins (LD[7:0]) to control
the FXS state and Switch state of up to eight SLIC devices. The SEL signal determines whether the P[2:0] value is
assigned to the FXS state of the SLIC device (SEL=0) or the Switch state of the SLIC device (SEL=1). The P[2:0]
and SEL values are latched inside the SLIC on the rising edge of the active low LD[n] signal. The P-BUS operates
continuously so that each channel’s FXS and Switch states are automatically refreshed every 128 ms.
2.6.9 Debug port
DEBUG_CLK requires a pull-up to the +1.8 V or the +3.3 V supply and DEBUG_IO requires a pull-down to DGND.
The most robust conditioning is to short DEBUG_CLK to +3.3 V and DEBUG_IO to DGND through 0 ohm resistors.
NGCC
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2.6.10 Sensitive Nodes
Highly sensitive analog nodes need to be protected from noise sources, especially noisy digital circuits. Sensitive
analog nodes of the SLAC and SLIC are highlighted in Figure 38. These nodes require special consideration when
routing, keep traces short and minimize vias. Components that have placement constraints are also shown,
position these components as described in Figure 38.
Figure 38 - SLAC-SLIC Interface - Sensitive Nodes
In addition, the P-bus, SEL, and LD timing signals (Figure 37) must be kept separate from the analog circuitry.
Avoid routing P-bus/SEL and LD timing signals near device pin areas unless route is on a different layer isolated by
a ground plane.
IB
IMTi
IBi
IAi
RCVPi
U2
Le79238 or
ZL79258
SLAC
RCVNi
VIMTi
VACi
CANCEL i
SVBi
SVAi
RCVPi
CM i
RCVNi
CCANi
CVACi
RSVB2i
RSVB1i
RSVA1i RSVA2i
VREFi
DCAi
CDCAi
CDCBi
DCBi
CVREFi
RCVP
IMT
IA
U1i
Le79271 or
Le79272
SLIC
RCVN
VREF
DCA
DCB
RIMTi
Keep trace < 10 pF
Keep trace < 20 pF
Keep trace < 20 pF
Keep traces < 5 pF
Position these
components close to
SLAC
Position these capacitors
close to SLIC
Notes:
i = channel number
Sensitive nodes (Blue).
Sensitive nodes with trace
capacitance restrictions (Red).
Keep all sensitive node leads
short and away from digital
sources.
To B lead
To A lead
Keep trace < 15 pF
Keep trace < 15 pF
XSBi
XSC
RSVB2i
RSVA2i
Keep trace < 20 pF
Keep trace < 20 pF
To Ringing
Feed
Resistor
To Ringing
Generator
ZL79258
SLAC
only
RDEBCLK
RDEBIO
DEBUG_IO
DEBUG_CLK
+3.3 V
Place these resistors
directly on SLAC
pins or BGA vias.
RST
CRST
This capacitor
is required for
external ringing
applications. Place
directly on SLAC
BGA via.
Reset
NGCC
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2.6.11 SLAC IO
The SLAC provides two general purpose programmable input/output pins per channel, IO[1:8]_0 and IO[1:8]_1.
The IO[1:8]_0 pins are configured to drive a 3 V coil electromechanical relay. The IO[1:8]_0 pins can be
programmed as open drain relay drivers. Built-in integrated flyback diodes eliminate the need for external diodes
across the relay coils. Refer to Figure 39 for a schematic representation. These pins are commonly used to drive
the calibration relay in Configuration D or the ringing relay for external ringing applications.
The other IO pins (IO[1:8]_1) are capable of sinking 10 mA when programmed as an output. These pins can be
used with an external transistor to drive a relay.
Figure 39 - SLAC Open Drain Relay Drivers
2.7 EMC Network
The AD/BD interface in Figure 37 shows two sets of EMI capacitors. The SLIC device only requires the C ADi and
CBDi capacitance values to satisfy 3 V RMS RF immunity requirements in a test board environment. However due to
PCB layout and component placement, often additional decoupling is required to satisfy EMC. Refer to the EMI
Capacitors Section 4.7 in Layout Considerations for more information on this topic.
The Host Test Library tests and accuracies assume a CADi and CBDi capacitance of 4.7 nF. If the capacitance
value on AD and BD leads is increased, change the Host Test Library header file to reflect the appropriate
capacitance value. The nominal capacitance from AD or BD to ground must be kept less than 10 nF.
For extensive information on EMC, request the Ve792 NGCC Electromagnetic Compatibility Application Note
(Document ID# 142651).
2.8 Using a Single Negative Battery
Referring to Figure 37, if only one negative battery is to be used. Tie the SLIC VBL pin directly to the SLIC VBH pin.
Do not connect VBL to the cathode side of D VBHi.
DGND_[1:6]
IO[1:8]_0
VDD33_[1:2]
Relay
coil
+3.3 V
supply
Le79238
or ZL79258
NGCC
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Microsemi Corporation Confidential and Proprietary
3.0 Application Circuits and Parts Lists
Components required external to the SLIC, SLAC, and VCP devices are detailed in the following Application
Circuits and Parts Lists. Use of the per channel test load and the metering capacitor are application dependent.
Most component values and tolerances are predefined for a given application and are not to be varied. The IVD
circuit varies dependant upon the application, so consult Microsemi for optimized components. Components that
are not discussed here are protection components, consult Microsemi for recommendations for your design.
Microsemi can provide part numbers for all the components listed in the Parts List.
The single channel Le79271 SLIC device can be substituted for the Le79272 Dual SLIC in any of the Application
Circuits.
If the Le79238 SLAC in the 164-pin LGA package is used, refer to Section 4.1.4 and Section 4.6 for layout and
connection information for its exposed pad.
Application circuits are provided for the supported hardware topologies. Parts Lists are provided for supported
calibration and test options for a given hardware topology. The hardware topologies and calibration circuit are
presented in detail in the various Software Package data sheets, as well as accuracies for the different test options.
Configuration C, D, E, and F topologies are supported. Configuration C is a basic internal ringing configuration.
Configuration D is similar but has the addition of an external relay to connect to a shared calibration circuit.
Configuration E is a basic external ringing configuration. Configuration F supports an external ringing application
that has an external relay to connect to a shared calibration circuit.
Figures 40-42 present application circuits for Configuration C. Figure 40 illustrates a POTS voice only application
using three batteries, BATP for ringing and boosted battery, BATH for ringing, scan, and off-hook DC feed for long
loops, and VBATL for off-hook DC feed for short loops. Figure 41 illustrates a voice only application circuit for short
loop applications like GPON using only two negative batteries, BATH for ringing and scan and VBATL for off-hook
DC feed. Figure 42 illustrates a voice and data (IVD) application using three batteries. Parts lists for these circuits
follow. Parts lists are provided for three test scenarios, Factory Calibration with Test, No Calibration with Test, and
No Calibration and No Test. Component tolerance is dependant upon the level of test and whether line card
calibration is used. Values, ratings, and proper tolerances for each of these scenarios is detailed in the respective
parts lists.
Figure 43 and Figure 44 present application circuits for Configuration D using three batteries. Figure 43 illustrates a
POTS voice only application circuit and Figure 44 illustrates a voice and data (IVD) application. Configuration D has
test capability and allows the line circuit to be calibrated when deployed. Values, ratings, and proper component
tolerances for this scenario is detailed in the Configuration D Parts List.
Figure 45 and Figure 46 illustrate POTS voice only application circuits for external ringing Configuration E. A
battery-backed and an earth-backed application are shown. This application use two batteries. Values, ratings, and
proper component tolerances are detailed in the Configuration E External Ringing Parts List.
Figure 47 and Figure 48 illustrate POTS voice only application circuits for external ringing Configuration F.
Configuration F has test capability and allows the line circuit to be calibrated when deployed. A battery-backed and
an earth-backed application are shown. This application use two batteries. Values, ratings, and proper component
tolerances are detailed in the Configuration F External Ringing Parts List.
Figure 49 shows the external components required for the Le79124 VCP device and Figure 50 shows the external
components required for the Le79234 VCP device. VCP GPI control and PCM connections using a single PCM
highway are illustrated. Figure 51 shows the external components required for the Le79128 VCP device. VCP GPI
control and PCM connections using dual PCM highways are illustrated. Component values, ratings, and tolerances
are detailed in the VCP Device Parts List. Note, any termination resistors used in the VCP to SLAC control
interface, as discussed in Section 2.4.1, are not shown in these Figures or Parts List.
NGCC
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Microsemi Corporation Confidential and Proprietary
3.1 Configuration C Application Circuits
Figure 40 - Configuration C - POTS Application
IMT
i
IB
i
IA
i
RCVPi
MPI and PCM
LD
i
P0
P1
P2
SHB
SLB
BATH
BATL
IREF
SPB
U2
Le79238
BATP
D
VBHi
A
B
SEL
RCVNi
VIMT
i
VAC
i
CANCEL
i
SVBi
SVAi
R
CVPi
C
M i
R
CVNi
R
IMTi
C
CANi
C
VACi
R
IREFi
R
SVB2i
R
SVB1i
R
SVA1i
R
SVA2i
R
SPB
R
SLB
R
SHB
R
REF
Channel 2
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 3
Channel 1
Required
for metering only
NOTES:
Transmission connections are shown for SLIC channel 1
and one SLAC channel where i = channel number.
* Optional components (Red).
** Consult Microsemi for optimized components (Blue).
*** Refer to Layout Considerations (Green).
*
See Absolute Maximum Ratings
Overcurrent/
Overvoltage
Protection
VREFi
DCAi
C
DCAi
C
DCBi
DCBi
C
VREFi
AVDDxx
+3.3 V
VDD33_x
DGND_x AGNDx
BATH
BATP
C
ADAi
C
BDBi
C
VDD18_x
VDD18_x +1.8 V
R
DEBIO
DEBUG_IO
C
FILT
+
C
AVDDxx
C
VDD33_x
DEBUG_CLK
R
DEBCLK
** FGND
LD
i
P0
P1
P2
LD1
VBH1
VBL1
RCVP1
IMT1
IA1
IB1
AGND1
+3.3 V
VCC1
BGND1
BATH
BATL
RIREF1
U1i
Le79272
VBP1
BATP
C
VCCi
SEL
RCVN1
C
BATHi
The exposed
thermal pad
should be
connected to
AGND or
BGND***
C
BATLi
C
BATPi
VREF1
DCA1
DCB1
AD1
TLD1
R
TESTi
*
C
ADi
BD1
C
BDi
*
*
VCC2
VBP2
VBH2
VBL2
BGND2 AGND2
LD2
NGCC
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49
Microsemi Corporation Confidential and Proprietary
Figure 42 - Configuration C - IVD Application
IMT
i
IB
i
IA
i
RCVPi
MPI and PCM
LD
i
SHB
SLB
BATH
BATL
IREF
SPB
U2
Le79238
BATP
A
B
AVDDxx
DGND_x AGNDx
+3.3 V
VDD33_x
RCVNi
VREFi
DCAi
VIMT
i
VAC
i
CANCEL
i
SVBi
SVAi
C
DCAi
R
CVPi
C
M i
R
CVNi
C
DCBi
R
IMTi
C
CANi
C
VACi
R
SVB2i
R
SVB1i
R
SVA1i
R
SVA2i
R
SPB
R
SLB
R
SHB
R
REF
Channel 2
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 3
Channel 1
Required
for metering only
C
SPi
L
SPi
**
xDSL DATA
MODEM
*
R
IREFi
P0
P1
P2
SEL
See Absolute Maximum Ratings
Overcurrent/
Overvoltage
Protection
DCBi
C
VREFi
C
ADAi
C
BDBi
C
VDD18_x
VDD18_x +1.8 V
R
DEBIO
DEBUG_IO
C
FILT
+
C
AVDDxx
C
VDD33_x
DEBUG_CLK
R
DEBCLK
*
*
**
**
FGND
P0
P1
P2
LD1
VBH1
VBL1
RCVP1
IMT1
IA1
IB1
AGND1
+3.3 V
VCC1
BGND1
BATH
BATL
RIREF1
U1i
Le79272
VBP1BATP
C
VCCi
SEL
RCVN1
C
BATHi
The exposed
thermal pad
should be
connected to
AGND or
BGND***
C
BATLi
C
BATPi
VREF1
DCA1
DCB1
AD1
TLD1
R
TESTi *
C
ADi
BD1
C
BDi
*
*
VCC2
VBP2
VBH2
VBL2
BGND2 AGND2
LD2 LD
i
NOTES:
Transmission connections are shown for SLIC channel 1
and one SLAC channel where i = channel number.
* Optional components (Red).
** Consult Microsemi for optimized components (Blue).
*** Refer to Layout Considerations (Green).
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3.2.3 No Calibration and No Test
The following list defines the parts and part values required to meet target specification limits for channel i of the line card.
(i = 1,2,3,4,5,6,7,8)
Item Type Tol.Value Min
Rating Comments Optional
Components
U1
i
Le79272 Dual SLIC device
U2 Le79238 Octal SLAC device
D
VBHi
Diode 200 mA 100 V
R
DEBCLK
, R
DEBIO
Resistor 0 Ω1/10 W
R
IMTi
Resistor 4.02 kΩ1% 1/16 W ±200 ppm/ºC
R
IREFi
Resistor 49.9 kΩ1% 1/16 W SLIC device current reference
R
REF
Resistor 75 kΩ0.5% 1/16 W SLAC device current reference, ±100 ppm/ºC
R
CVPi,
R
CVNi
Resistor 562 Ω1% 1/16 W
R
SVA1i
, R
SVA2i
,
R
SVB1i
, R
SVB2i
Resistor 1.62 MΩ1.0% 500 V A/B sense resistors, ±200 ppm/ºC
R
SHB
, R
SLB
, R
SPB
Resistor 1.62 MΩ1% 150 V Battery sense resistors
R
TESTi
Resistor 2 k
Ω
1% 1 W Test load Optional, for testing
C
ADi
, C
BDi
Capacitor 4.7 nF 10% 200 V
Ceramic, chip, X7R, EMI capacitor. Refer to
Section 2.7 and Section 4.7 for more
information.
C
ADAi
, C
BDBi
Capacitor 4.7 nF 10% 200 V
Ceramic, chip, X7R, EMI capacitor. Refer to
Section 2.7 and Section 4.7 for more
information.
Optional, for EMC
C
BATHi
, C
BATLi
,
C
BATPi
Capacitor 100 nF 20% 100 V Ceramic, chip, X7R. Voltage rating needs to
exceed battery voltage.
C
BATPi
not required
for negative battery
only applications
C
FILT
Capacitor 10 μF 20% 6.3 V Ceramic or tantalum
C
CANi
Capacitor 2.2 nF 10% 6.3 V Metering capacitor Optional, for metering
C
DCAi
, C
DCBi
Capacitor 220 nF 10% 6.3 V Ceramic, chip, X7R
C
VACi
Capacitor 100 nF 20% 6.3 V Ceramic, chip, X7R
C
VCCi
, C
VDD18_x
,
C
VDD33_x
, C
AVDDxx
Capacitor 100 nF 20% 6.3 V Ceramic, chip, X7R, on SLAC device use one
decoupling capacitor for each supply pin
C
VREFi
Capacitor 470 nF 20% 6.3 V Ceramic, chip, X7R
C
Mi
Capacitor 4.7 nF 10% 6.3 V Ceramic, chip, X7R
C
SPi
Capacitor 33 nF 10% 400 V Metallized film, withstand voltage of 600 VRMS Optional, for IVD
application, contact
Microsemi
L
SPi
Inductor
NGCC
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Microsemi Corporation Confidential and Proprietary
Figure 44 - Configuration D - IVD Application
IMT
i
IB
i
IA
i
RCVPi
MPI and PCM
LD
i
SHB
SLB
BATH
BATL
IREF
SPB
U2
Le79238
BATP
AVDDxx
DGND_x AGNDx
+3.3 V
VDD33_x
RCVNi
VREFi
DCAi
VIMT
i
VAC
i
CANCEL
i
SVBi
SVAi
C
DCAi
R
CVPi
C
M i
R
CVNi
C
DCBi
R
IMTi
C
CANi
C
VACi
R
SVB2i
R
SVB1i
R
SVA1i
R
SVA2i
R
SPB
R
SLB
R
SHB
R
REF
Channel 2
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 3
Channel 1
Required
for metering only
*
R
IREFi
P0
P1
P2
SEL
See Absolute Maximum Ratings
Overcurrent/
Overvoltage
Protection
DCBi
C
VREFi
A
B
C
SPi
xDSL
DATA
MODEM
CALIBRATION
BUS
K
CALi
+3.3 V IOi_0
IOi_0 IOi_0
C
ADAi
C
BDBi
C
VDD18_x
VDD18_x +1.8 V
R
DEBIO
DEBUG_IO
C
FILT
+
C
AVDDxx
C
VDD33_x
DEBUG_CLK
R
DEBCLK
*
*
**
**
FGND
L
SPi
**
NOTES:
Transmission connections are shown for SLIC channel 1
and one SLAC channel where i = channel number.
* Optional components (Red).
** Consult Microsemi for optimized components (Blue).
*** Refer to Layout Considerations (Green).
P0
P1
P2
LD1
VBH1
VBL1
RCVP1
IMT1
IA1
IB1
AGND1
+3.3 V
VCC1
BGND1
BATH
BATL
RIREF1
U1i
Le79272
VBP1BATP
C
VCCi
SEL
RCVN1
C
BATHi
The exposed
thermal pad
should be
connected to
AGND or
BGND***
C
BATLi
C
BATPi
VREF1
DCA1
DCB1
AD1
TLD1
R
TESTi
*
C
ADi
BD1
C
BDi
*
*
VCC2
VBP2
VBH2
VBL2
BGND2 AGND2
LD2 LD
i
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Design Guide
55
Microsemi Corporation Confidential and Proprietary
3.4 Configuration D Parts List
3.4.1 In-Service Calibration and Test
The following list defines the parts and part values required to meet target specification limits for channel i of the line card.
(i = 1,2,3,4,5,6,7,8)
Item Type Tol.Value Min
Rating Comments Optional
Components
U1
i
Le79272 Dual SLIC device
U2 Le79238 Octal SLAC device
K
CALi
DPDT
Relay 3 V Test-In relay
D
VBHi
Diode 200 mA 100 V
R
DEBCLK
, R
DEBIO
Resistor 0 Ω1/10 W
R
IMTi
Resistor 4.02 kΩ1% 1/16 W ±200 ppm/ºC
R
IREFi
Resistor 49.9 kΩ1% 1/16 W SLIC device current reference
R
REF
Resistor 75 kΩ0.5% 1/16 W SLAC device current reference, ±100 ppm/ºC
R
CVPi,
R
CVNi
Resistor 562 Ω1% 1/16 W
R
SVA1i
, R
SVA2i
,
R
SVB1i
, R
SVB2i
Resistor 1.62 MΩ1.0% 500 V A/B sense resistors, ±200 ppm/ºC
R
SHB
, R
SLB
, R
SPB
Resistor 1.62 MΩ1% 150 V Battery sense resistors
R
TESTi
Resistor 2 k
Ω
1% 1 W Test load Optional, for testing
C
ADi
, C
BDi
Capacitor 4.7 nF 10% 200 V
Ceramic, chip, X7R, EMI capacitor. Refer to
Section 2.7 and Section 4.7 for more
information.
C
ADAi
, C
BDBi
Capacitor 4.7 nF 10% 200 V
Ceramic, chip, X7R, EMI capacitor. Refer to
Section 2.7 and Section 4.7 for more
information.
Optional, for EMC
C
BATHi
, C
BATLi
,
C
BATPi
Capacitor 100 nF 20% 100 V Ceramic, chip, X7R. Voltage rating needs to
exceed battery voltage.
C
FILT
Capacitor 10 μF 20% 6.3 V Ceramic or tantalum
C
CANi
Capacitor 2.2 nF 10% 6.3 V Metering capacitor Optional, for metering
C
DCAi
, C
DCBi
Capacitor 220 nF 10% 6.3 V Ceramic, chip, X7R
C
VACi
Capacitor 100 nF 20% 6.3 V Ceramic, chip, X7R
C
VCCi
, C
VDD18_x
,
C
VDD33_x
, C
AVDDxx
Capacitor 100 nF 20% 6.3 V Ceramic, chip, X7R, on SLAC device use one
decoupling capacitor for each supply pin
C
VREFi
Capacitor 470 nF 20% 6.3 V Ceramic, chip, X7R
C
Mi
Capacitor 4.7 nF 10% 6.3 V Ceramic, chip, X7R
C
SPi
Capacitor 33 nF 10% 400 V Metallized film, withstand voltage of 600 VRMS Optional, for IVD
application, contact
Microsemi
L
SPi
Inductor
NGCC
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Microsemi Corporation Confidential and Proprietary
3.5 Configuration E External Ringing Application Circuits
Figure 45 - Configuration E - Battery-Backed Ringing POTS Application
NGCC
Design Guide
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Microsemi Corporation Confidential and Proprietary
3.6.2 No Calibration with Test
The following list defines the parts and part values required to meet target specification limits for channel i of the line card.
(i = 1,2,3,4,5,6,7,8)
C
RST
Capacitor 1000 pF 10% 6.3 V Ceramic, chip, X7R
* Component’s voltage specification depends on ringing voltage, surge requirement, and ringing bus protection.
** The Ringing/Reset relay can be used to disconnect the SLIC from the line to test foreign voltages if the Ringing Bus relay is actuated (no
ringing signal applied). To implement this feature, it is advantageous to use multiple Ringing Bus relays to minimize the impact of testing on
provisioned lines.
Item Type Tol.Value Min
Rating Comments Optional
Components
U1
i
Le79272 Dual SLIC device
U2 ZL79258 Octal SLAC device
K1
i
DPDT 3 V Ringing/Reset relay
K2 DPDT 3 V Ringing Bus relay **
D
VBHi
Diode 200 mA 100 V
R
DEBCLK
, R
DEBIO
Resistor 0 Ω1/10 W
R
FEEDi
Resistor 510 Ω5% 2 W Ringing feed resistor, high voltage wirewound *Use for battery-
backed ringing
R
EBFi
Resistor 200 Ω5% 1 W Ringing feed resistor, high voltage wirewound *Use for earth-backed
ringing
R
EBRi
Resistor 450 Ω5% 1 W Ringing return resistor, high voltage wirewound *
R
IMTi
Resistor 4.02 kΩ1% 1/16 W ±200 ppm/ºC
R
IREFi
Resistor 49.9 kΩ1% 1/16 W SLIC device current reference
R
REF
Resistor 75 kΩ0.5% 1/16 W SLAC device current reference, ±100 ppm/ºC
R
CVPi,
R
CVNi
Resistor 562 Ω1% 1/16 W
R
SVA1i
, R
SVA2i
,
R
SVB1i
, R
SVB2i
Resistor 1.62 MΩ0.5% 500 V A/B sense resistors, ±200 ppm/ºC
R
SHB
, R
SLB
Resistor 1.62 MΩ1% 150 V Battery sense resistors
R
TESTi
Resistor 2 k
Ω
1% 1 W Test load Optional, for testing
R
SNAi
, R
SNBi
,
R
SNAR
, R
SNBR
Resistor 1.0 kΩ1% 1/8 W Snubber resistor
R
XSB1i
, R
XSC1
Resistor 887 kΩ1% 1/4 W Ringing sense resistors, high voltage,
surge rated *
R
XSB2i
, R
XSC2
Resistor 732 kΩ1% 1/4 W
C
SNAi
,
C
SNAR
Capacitor 100 nF 20%
100 V
Snubber capacitor. Ceramic, chip, X7R.
Use for battery-
backed ringing
C
SNBi
,
C
SNBR
200 V
C
SNAi
,
C
SNAR
200 V Use for earth-backed
ringing
C
SNBi
,
C
SNBR
100 V
C
ADi
, C
BDi
Capacitor 4.7 nF 5% 200 V Ceramic, chip, X7R, EMI capacitor. Refer to
Section 2.7 and Section 4.7 for more
information.
C
ADAi
, C
BDBi
Capacitor 4.7 nF 5% 200 V Optional, for EMC
C
BATHi
, C
BATLi
Capacitor 100 nF 20% 100 V Ceramic, chip, X7R. Voltage rating needs to
exceed battery voltage.
C
FILT
Capacitor 10 μF 20% 6.3 V Ceramic or tantalum
C
CANi
Capacitor 2.2 nF 10% 6.3 V Metering capacitor Optional, for metering
C
DCAi
, C
DCBi
Capacitor 220 nF 10% 6.3 V Ceramic, chip, X7R
C
VACi
Capacitor 100 nF 20% 6.3 V Ceramic, chip, X7R
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Microsemi Corporation Confidential and Proprietary
C
CANi
Capacitor 2.2 nF 10% 6.3 V Metering capacitor Optional, for metering
C
DCAi
, C
DCBi
Capacitor 220 nF 10% 6.3 V Ceramic, chip, X7R
C
VACi
Capacitor 100 nF 20% 6.3 V Ceramic, chip, X7R
C
VCCi
, C
VDD18_x
,
C
VDD33_x
, C
AVDDxx
Capacitor 100 nF 20% 6.3 V Ceramic, chip, X7R, on SLAC device use one
decoupling capacitor for each supply pin
C
VREFi
Capacitor 470 nF 20% 6.3 V Ceramic, chip, X7R
C
Mi
Capacitor 4.7 nF 10% 6.3 V Ceramic, chip, X7R
C
RST
Capacitor 1000 pF 10% 6.3 V Ceramic, chip, X7R
* Component’s voltage specification depends on ringing voltage, surge requirement, and ringing bus protection.
** The Ringing/Reset relay can be used to disconnect the SLIC from the line to test foreign voltages if the Ringing Bus relay is actuated (no
ringing signal applied). To implement this feature, it is advantageous to use multiple Ringing Bus relays to minimize the impact of testing on
provisioned lines.
NGCC
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Microsemi Corporation Confidential and Proprietary
Figure 48 - Configuration F - Earth-Backed Ringing Application
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Microsemi Corporation Confidential and Proprietary
3.8 Configuration F External Ringing Parts List
3.8.1 In-Service Calibration and Test
The following list defines the parts and part values required to meet target specification limits for channel i of the line card.
(i = 1,2,3,4,5,6,7,8)
Item Type Tol.Value Min
Rating Comments Optional
Components
U1
i
Le79272 Dual SLIC device
U2 ZL79258 Octal SLAC device
K1
i
DPDT 3 V Ringing/Reset relay
K2 DPDT 3 V Ringing Bus relay **
K
CALi
DPDT 3 V Test-In relay
Relay Driver Or equivalent circuitry
D
VBHi
Diode 200 mA 100 V
R
DEBCLK
, R
DEBIO
Resistor 0 Ω1/10 W
R
FEEDi
Resistor 510 Ω5% 2 W Ringing feed resistor, high voltage wirewound *Use for battery-
backed ringing
R
EBFi
Resistor 200 Ω5% 1 W Ringing feed resistor, high voltage wirewound *Use for earth-backed
ringing
R
EBRi
Resistor 450 Ω5% 1 W Ringing return resistor, high voltage wirewound *
R
IMTi
Resistor 4.02 kΩ1% 1/16 W ±200 ppm/ºC
R
IREFi
Resistor 49.9 kΩ1% 1/16 W SLIC device current reference
R
REF
Resistor 75 kΩ0.5% 1/16 W SLAC device current reference, ±100 ppm/ºC
R
CVPi,
R
CVNi
Resistor 562 Ω1% 1/16 W
R
SVA1i
, R
SVA2i
,
R
SVB1i
, R
SVB2i
Resistor 1.62 MΩ1.0% 500 V A/B sense resistors, ±200 ppm/ºC
R
SHB
, R
SLB
Resistor 1.62 MΩ1% 150 V Battery sense resistors
R
TESTi
Resistor 2 k
Ω
1% 1 W Test load Optional, for testing
R
SNAi
, R
SNBi
,
R
SNAR
, R
SNBR
Resistor 1.0 kΩ1% 1/8 W Snubber resistor
R
XSB1i
, R
XSC1
Resistor 887 kΩ1% 1/4 W Ringing sense resistors, high voltage,
surge rated *
R
XSB2i
, R
XSC2
Resistor 732 kΩ1% 1/4 W
C
SNAi
,
C
SNAR
Capacitor 100 nF 20%
100 V
Snubber capacitor. Ceramic, chip, X7R.
Use for battery-
backed ringing
C
SNBi
,
C
SNBR
200 V
C
SNAi
,
C
SNAR
200 V Use for earth-backed
ringing
C
SNBi
,
C
SNBR
100 V
C
ADi
, C
BDi
Capacitor 4.7 nF 10% 200 V Ceramic, chip, X7R, EMI capacitor. Refer to
Section 2.7 and Section 4.7 for more
information.
C
ADAi
, C
BDBi
Capacitor 4.7 nF 10% 200 V Optional, for EMC
C
BATHi
, C
BATLi
Capacitor 100 nF 20% 100 V Ceramic, chip, X7R. Voltage rating needs to
exceed battery voltage.
C
FILT
Capacitor 10 μF 20% 6.3 V Ceramic or tantalum
C
CANi
Capacitor 2.2 nF 10% 6.3 V Metering capacitor Optional, for metering
C
DCAi
, C
DCBi
Capacitor 220 nF 10% 6.3 V Ceramic, chip, X7R
C
VACi
Capacitor 100 nF 20% 6.3 V Ceramic, chip, X7R
C
VCCi
, C
VDD18_x
,
C
VDD33_x
, C
AVDDxx
Capacitor 100 nF 20% 6.3 V Ceramic, chip, X7R, on SLAC device use one
decoupling capacitor for each supply pin
NGCC
Design Guide
65
Microsemi Corporation Confidential and Proprietary
C
VREFi
Capacitor 470 nF 20% 6.3 V Ceramic, chip, X7R
C
Mi
Capacitor 4.7 nF 10% 6.3 V Ceramic, chip, X7R
C
RST
Capacitor 1000 pF 10% 6.3 V Ceramic, chip, X7R
* Component’s voltage specification depends on ringing voltage, surge requirement, and ringing bus protection.
** The Ringing/Reset relay can be used to disconnect the SLIC from the line to test foreign voltages if the Ringing Bus relay is actuated (no
ringing signal applied). To implement this feature, it is advantageous to use multiple Ringing Bus relays to minimize the impact of testing on
provisioned lines.
NGCC
Design Guide
66
Microsemi Corporation Confidential and Proprietary
3.9 VCP Device Application Circuits
Figure 49 - Le79124 VCP External Components
PD0
FSA
PCLKA
Host
Processor
Le79238
Le79238
Le79124
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PADDR
PCS
CONF0
CONF2
CONF1
DVDD
DVSS
PCLK
FS
DRA
DXA
DXA
DRA
SYS_PCLK
SYS_FS
SYS_DX
SYS_DR
CVDD
Network Interface
Notes:
VDD18CTRL
+3.3 V
VDD18 +1.8 V
PWAIT
Le79238
Le79238
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
PCLK
FS
DRA
DXA
Le79238
Le79238
Le79238
Le79238
PLL_VSS
PLL_VDD
RPWAIT
+3.3 V
- Optional component in red.
- For signal integrity, provide PCM bus termination and buering accordingly.
U1
U2
U3
U4
U5
U6
U7
U8
Le79238
PCLK
FS
DRA
DXA
U9
PWR
PRD
- 16-bit parallel with separate read and write strobe GPI control shown.
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
PCLKB
DXB
DRB
FSB
MPCLK
MFS
MDX
MDR
Slave
PCM
Highway
A
GPI
RSTZ
RSTZ
CVDD18 CFILT
RSTZ
TRST RTRST
+
RST
To SLACs
+3.3 V
RUP
RUP
NGCC
Design Guide
68
Microsemi Corporation Confidential and Proprietary
Figure 51 - Le79128 VCP External Components
Le79128
DRA
FSA
DXA
PCLKA
FS
PCLK
DRA
DXA
U1
U8
MDX
Le79238
MFS
MPCLK
MDR
FS
PCLK
DRB
DXB
U9
Le79238
U16
Le79238
Le79238
SYS_PCLK1
SYS_FS1
SYS_DX1
SYS_DR1
Network Interface
+3.3 V
RUP
PCM Highway 1
RSTZ
FS
PCLK
DRA
DXA
RSTZ
RSTZ RSTZ
PCM Highway 2
SYS_PCLK2
SYS_FS2
SYS_DX2
SYS_DR2
RUP
RSTZ
RSTZ
FS
PCLK
DRB
DXB
Slave PCM
Highway A
Slave PCM
Highway B
PCLKB
FSB
DRB
DRB
DRA
DRA
PD0
Host
Processor
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PADDR
PCS
PWAIT
RPWAIT
PWR
PRD
GPI
RST
To SLACs
DVSS
VDD18CTRL
VDD18 +1.8 V
PLL_VSS
+3.3 V
DXB
DRB
CVDD18 CFILT
+
CONF0
CONF2
CONF1
DVDD
CVDD
+3.3 V
PLL_VDD
TRST
RTRST
Notes:
- Optional component (in red).
- For signal integrity, provide PCM bus
termination and buering accordingly.
- 16-bit parallel with separate read and
write strobe GPI control shown.
+3.3 V +3.3 V
RUP
RUP
NGCC
Design Guide
69
Microsemi Corporation Confidential and Proprietary
3.9.1 VCP Device Parts List
The following table lists the external components required for the VCP device and the PCM highway as shown in the Application
Circuits.
Item Qty Type Value Tol. Rating Comments
C
FILT
1 Capacitor 10 μF 20% 6.3 V Ceramic or tantalum
C
VDD
9 Capacitor 100 nF 20% 10 V Ceramic
C
VDD18
4 Capacitor 100 nF 20% 10 V Ceramic
R
UP
2 or 4 Resistor 10 KΩ10% 1/16 W Use 2 per PCM Highway
R
STZ
5 or 10 Resistor 39 10% 1/16 WΩ
Use 1 set per PCM Highway.
Select appropriate value for
transmission line.
R
TRST
1 Resistor 1 KΩ10% 1/16 W Refer to Section 2.2.2 for debug
port options.
R
RSVD
2 Resistor 10 KΩ10% 1/16 W Required for Le79234 device only
R
PWAIT
1 Resistor 10 KΩ10% 1/16 W Required if PWAIT is used
NGCC
Design Guide
76
Microsemi Corporation Confidential and Proprietary
Table 4 - Le51HR0140 Board Layers
The Le51HR0140 board layout is shown in Figure 58. The Le51HR0140 has 9 groups of 8 channels of SLIC
devices. Each grouping of 8 SLIC devices surrounds the SLAC emulating SLIC device in the hub arrangement. The
grouping numbers are identified in Figure 58. The thermal pad layout used on all the SLIC devices is as illustrated
in Figure 53. Note that the 176-pin LQFP SLAC footprint is shown for placement spacing only, the SLAC emulating
SLIC device is centered in the hub arrangement.
Layer Name Material Thickness mil Copper Pour
Top Copper 0.7 No
Laminate FR408 8 -
Ground 1 Copper 0.7 Yes
Laminate FR408 8 -
Signal 1 Copper 0.7 Yes
Laminate FR408 8 -
Power 1 Copper 0.7 Yes
Laminate FR408 8 -
Signal 2 Copper 0.7 Yes
Laminate FR408 8 -
Signal 3 Copper 0.7 Yes
Laminate FR408 8 -
Power 2 Copper 0.7 Yes
Laminate FR408 8 -
Signal 4 Copper 0.7 Yes
Laminate FR408 8 -
Ground 2 Copper 0.7 Yes
Laminate FR408 8 -
Bottom Copper 0.7 No
NGCC
Design Guide
77
Microsemi Corporation Confidential and Proprietary
Figure 58 - Le51HR0140 Groupings and Board Layout
4.3.1.2 Electrical Set-up
For the following experiment:
Loop current for SLIC devices in groups 1-4 and 6-9 were set to 24 mA using a high battery of -52 V. Power dissi-
pation of a SLIC in the off-hook active state with a short loop under this condition is 0.8 W.
Loop current for SLIC devices in group 5 were set to 40 mA using a high battery of -52 V. Power dissipation of a
SLIC in the off-hook active state with a short loop under this condition is 1.2 W.
Power dissipation for all SLAC emulating SLIC devices was set to 0.85 Watts.
4.3.1.3 Wind Tunnel Design
To enable controlled airflow measurements a wind tunnel was created. The wind tunnel is pictured in Figure 59. On
the side of the wind tunnel there is an opening to allow for the load/power board to connect to the Le51HR0140
board under test.

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Model: LE79272

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