Microchip PIC24FJ32GA002 Manual

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 2007-2015 Microchip Technology Inc. DS70000195G-page 1

HIGHLIGHTS

This section of the manual contains the following major topics:

1.0 Introduction ....................................................................................................................... 2

2.0 I

C Bus Characteristics..................................................................................................... 4

3.0 Control and Status Registers ............................................................................................ 8

4.0 Enabling I

C Operation ................................................................................................... 18

5.0 Communicating as a Master in a Single Master Environment ........................................ 20

6.0 Communicating as a Master in a Multi-Master Environment .......................................... 34

7.0 Communicating as a Slave ............................................................................................. 37

8.0 Connection Considerations for I

C Bus .......................................................................... 61

9.0 Operation in Power-Saving Modes ................................................................................. 63

10.0 Peripheral Module Disable (PMDx) Registers ................................................................ 63

11.0 Effects of a Reset............................................................................................................ 63

12.0 Constant-Current Source ................................................................................................ 64

13.0 Register Maps................................................................................................................. 66

14.0 Design Tips ..................................................................................................................... 67

15.0 Related Application Notes............................................................................................... 68

16.0 Revision History .............................................................................................................. 69

Inter-Integrated Circuit (I2C)

dsPIC33/PIC24 Family Reference Manual

DS70000195G-page 2  2007-2015 Microchip Technology Inc.

This document supersedes the following PIC24 and dsPIC

DSC Family Reference Manual sections:

1.0 INTRODUCTION

The Inter-Integrated Circuit (I

C) module is a serial interface useful for communicating with other

peripheral or microcontroller (MCU) devices. The external peripheral devices may be serial

EEPROMs, display drivers, Analog-to-Digital Converters (ADC) and so on.

The I

C module can operate as any one of the following in the I

C system:

• Slave device

• Master device in a single master system (slave may be active)

• Master or slave device in a multi-master system (bus collision detection and arbitration are

available)

The I

C module contains an independent I

C master logic and a I

C slave logic, which generates

interrupts based on their events. In the multi-master systems, the user software is simply

partitioned into the master controller and the slave controller.

When the I

C master logic is active, the slave logic also remains active, detecting the state of the

bus and potentially receiving messages from itself in a single master system or from the other

masters in a multi-master system. No messages are lost during the multi-master bus arbitration.

In a multi-master system, the bus collision conflicts with the other masters in the system when

detected, and the module provides a method to terminate and then restart the message.

The I

C module contains a Baud Rate Generator (BRG). The I

C BRG does not consume other

timer resources in the device. Figure 1-1 illustrates the I

C module block diagram.

Key features of the I

C module include the following:

• Independent master and slave logic

• Multi-master support which prevents message losses in arbitration

• Detects 7-bit and 10-bit device addresses with configurable address masking in Slave mode

• Detects general call addresses as defined in the I

C protocol

• Bus Repeater mode, allowing the module to accept all messages as a slave, irrespective of

the address

• Automatic SCLx clock stretching provides delays for the processor to respond to a slave

data request

• Supports 100 kHz and 400 kHz bus specifications

• Supports the Intelligent Platform Management Interface (IPMI) standard

• Supports SDAx hold time for SMBus (300 nS or 150 nS) in Slave mode

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC24 and dsPIC33 devices.

Please consult the note at the beginning of the “Inter-Integrated Circuit (I

C)”

chapter in the current device data sheet to check whether this document supports

the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at:

http://www.microchip.com

DS Number Section Number Title

DS70195 19 dsPIC33F/PIC24H Family Reference Manual

DS70330 19 dsPIC33E/PIC24E Family Reference Manual

DS39702 24 PIC24F Family Reference Manual

DS70235 19 PIC24H Family Reference Manual

DS70068 21 dsPIC30F Family Reference Manual

Note:

For more information, refer to the SDAHT bit description in the specific device data sheet.

Produkt Specifikationer

Mærke:	Microchip
Kategori:	Ikke kategoriseret
Model:	PIC24FJ32GA002

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