Microchip PIC24FJ64GA002 Manual
Microchip
Ikke kategoriseret
PIC24FJ64GA002
Læs gratis den danske manual til Microchip PIC24FJ64GA002 (42 sider) i kategorien Ikke kategoriseret. Denne vejledning er vurderet som hjælpsom af 13 personer og har en gennemsnitlig bedømmelse på 4.6 stjerner ud af 7 anmeldelser. Har du et spørgsmål om Microchip PIC24FJ64GA002, eller vil du spørge andre brugere om produktet?
Side 1/42
© 2009 Microchip Technology Inc. DS39705B-page 17-1
10-Bit A/D
Converter
17
Section 17. 10-Bit A/D Converter
HIGHLIGHTS
This section of the manual contains the following major topics:
17.1 Introduction ................................................................................................................. 17-2
17.2 A/D Terminology and Conversion Sequence .............................................................. 17-4
17.3 Registers..................................................................................................................... 17-6
17.4 A/D Module Configuration ......................................................................................... 17-13
17.5 Initialization ............................................................................................................... 17-16
17.6 Controlling the Sampling Process............................................................................. 17-17
17.7 Controlling the Conversion Process.......................................................................... 17-17
17.8 A/D Results Buffer..................................................................................................... 17-23
17.9 Conversion Sequence Examples.............................................................................. 17-25
17.10 A/D Sampling Requirements..................................................................................... 17-33
17.11 Transfer Function ...................................................................................................... 17-34
17.12 A/D Accuracy/Error ................................................................................................... 17-35
17.13 Operation During Sleep and Idle Modes................................................................... 17-35
17.14 Effects of a Reset...................................................................................................... 17-36
17.15 Register Maps........................................................................................................... 17-37
17.16 Electrical Specifications............................................................................................. 17-38
17.17 Design Tips ............................................................................................................... 17-39
17.18 Related Application Notes......................................................................................... 17-40
17.19 Revision History ........................................................................................................ 17-41
PIC24F Family Reference Manual
DS39705B-page 17-2 © 2009 Microchip Technology Inc.
17.1 INTRODUCTION
The PIC24F 10-bit A/D Converter has the following key features:
• Successive Approximation Register (SAR) Conversion
• Conversion Speeds of up to 500 ksps
• Up to 16 External Analog Input Channels
• Multiple Internal Reference Input Channels (select devices only)
• External Voltage Reference Input Pins
• Unipolar Differential Sample-and-Hold (S/H) Amplifier
• Automatic Channel Scan mode
• Selectable Conversion Trigger Source
• 16-Word Conversion Result Buffer
• Selectable Buffer Fill modes
• Four Options for Results Alignment
• Operation during CPU Sleep and Idle modes
The 10-bit A/D Converter module accepts a single analog signal at any one instant and converts
it to a corresponding 10-bit digital value. It accomodates up to 16 analog inputs and separate ref-
erence inputs; the actual number available on a particular device depends on the package size.
The heart of the module is a Successive Approximation Register (SAR) type of A/D Converter.
Hardware features surrounding the SAR provide flexible configuration and hardware support for
automatic operation, and minimize software overhead, especially in high-speed operation. The
three major sections surrounding the ADC are analog input selection, a memory mapped output
buffer, and timing and control functions.
An internal Sample-and-Hold (S/H) amplifier acquires a sample of an input signal, then holds that
value constant during the conversion process. A combination of input multiplexers selects the
signal to be converted from multiple analog input pins. The whole multiplexer path includes pro-
vision for differential analog input, although the number of negative input pins is limited, and the
signal difference must remain positive (i.e., unipolar). The sampled voltage is held and converted
to a digital value, which strictly speaking, represents the ratio of that input voltage to a reference
voltage. Configuration choices allow connection of an external reference or use of the device
power and ground (AVDD and AVSS). Reference and input signal pins are assigned differently
depending on the particular device.
An array of timing and control selections allow the user to create flexible scanning sequences.
Conversions can be started individually by program control, continuously free running, or triggered
by selected hardware events. A single channel may be repeatedly converted; alternate conver-
sions may be performed on two channels, or any or all of the channels may be sequentially
scanned and converted according to a user-defined bit map. The resulting conversion output is a
10-bit digital number which can be signed or unsigned, left or right justified.
Conversions are automatically stored in a dedicated 16-word buffer, allowing for multiple succes-
sive readings to be taken before software service is needed. Successive conversions are placed
into sequential buffer locations. Alternatively, the buffer can be split into two 8-word sections for
simultaneous conversion and read operations. The module sets its interrupt flag after a selectable
number of conversions, from one to sixteen, when the whole buffer can be read. After the interrupt,
the sequence restarts at the beginning of the buffer. When the interrupt flag is set according to the
earlier selection, scan selections and the Output Buffer Pointer return to their starting positions.
A simplified block diagram for the module is shown in Figure 17-1.
© 2009 Microchip Technology Inc. DS39705B-page 17-3
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
Figure 17-1: 10-Bit A/D Converter Block Diagram
Comparator
10-Bit SAR Conversion Logic
V +REF
DAC
AN12
AN13
AN14
AN15
AN8
AN9
AN10
AN11
AN4
AN5
AN6
AN7
AN0
AN1
AN2
AN3
V -REF
Sample Control
S/H
AVSS
AVDD
ADC1BUF0:
ADC1BUFF
AD1CON1
AD1CON2
AD1CON3
AD1CHS
AD1PCFG(L)
AD1PCFGH (2)
Control Logic
Data Formatting
Input MUX Control
Conversion Control
Pin Config. Control
Internal Data Bus
16
V +V - RR
MUX AMUX B
VINH
VINL
VINH
VINH
VINL
VINL
VR+
VR-
VR Select
VBG(1)
VBG/2(1)
AD1CSSL
AD1CSSH(2)
Note 1: Internal analog channels are implemented in select devices only. Different device families implement different
combinations of channels. Refer to the specific device data sheet for details.
2: Implemented in select devices only.
CTMU(1)
VDDCORE(1)
AVSS(1)
AVDD(1)
PIC24F Family Reference Manual
DS39705B-page 17-4 © 2009 Microchip Technology Inc.
17.2 A/D TERMINOLOGY AND CONVERSION SEQUENCE
Sample time is the time that the A/D module’s S/H amplifier is connected to the analog input pin.
The sample time may be started and ended automatically by the A/D Converter’s hardware or
under direct program control. There is a minimum sample time to ensure that the S/H amplifier
will give sufficient accuracy for the A/D conversion.
Conversion time is the time required for the A/D Converter to convert the voltage held by the
S/H amplifier. The conversion trigger ends the sampling time and begins an A/D conversion or a
repeating sequence. The conversion trigger sources can be taken from a variety of hardware
sources or can be controlled directly in software. An A/D conversion requires one A/D clock cycle
(TAD) to convert each bit of the result, plus two additional clock cycles, or a total of 12 TAD cycles
for a 10-bit conversion. When the conversion is complete, the result is loaded into one of 16 A/D
result buffers. The S/H can be reconnected to the input pin and a CPU interrupt may be gener-
ated. The sum of the sample time and the A/D conversion time provides the total A/D sequence
time. Figure 17-2 shows the basic conversion sequence and the relationship between intervals.
The conversion trigger sources can be taken from a variety of hardware sources, or can be
controlled directly by software. One of the conversion trigger options is an auto-conversion,
which uses a counter and the A/D clock to set the time between auto-conversions. The
Auto-Sample mode and auto-conversion trigger can be used together to provide continuous
automatic conversions without software intervention.
Figure 17-2: A/D Sample/Convert Sequence
Sample Time A/D Conversion Time
Total A/D Sequence Time
S/H amplifier is connected to
the analog input pin for sampling.
Input disconnected; S/H amplifier holds signal.
Conversion trigger starts A/D conversion.
Conversion complete, result is loaded
into A/D Buffer register.
Interrupt is generated (optional).
© 2009 Microchip Technology Inc. DS39705B-page 17-5
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
17.2.1 Operation as a State Machine
The A/D conversion process can be thought of in terms of a finite state machine (Figure 17-3).
The sample state represents the time that the input channel is connected to the S/H amplifier and
the signal is passed to the converter input. The convert state is transitory; the module enters this
state as soon as it exits the sample state and transitions to a different state when that is done.
The inactive state is the default state prior to module initialization and following a
software-controlled conversion; it can be avoided in operation by using Auto-Sample mode.
Machine states are identified by the state of several control and status bits in AD1CON1
(Register 17-1).
If the module is configured for Auto-Sample mode, the operation “ping-pongs” continuously
between the sample and convert states. The module automatically selects the input channels to
be sampled (if channel scanning is enabled), while the selected conversion trigger source paces
the entire operation. Any time that Auto-Sample mode is not used for conversion, it is available
for the sample state.The user needs to make certain that acquisition time is sufficient, in addition
to accounting for the normal concerns about system throughput.
Whenever the issue of sampling time is important, the significant event is the transition from
sample to convert state. This is the point where the Sample-and-Hold aperture closes and it is
essentially the signal value at this instant which is applied to the A/D for conversion to digital.
Figure 17-3: A/D Module State Machine Model
INACTIVE
SAMPLE CONVERT
SAMP = 0
DONE = 1
SAMP = 0
DONE =
0
SAMP = 1
DONE = x
SAMP 0→1
ASAM = 1 and DONE 0 1→
ASAM = 0 and
SSRC Trigger Events (see table)
DONE 0→1
SSRC Trigger Events
SSRC<2:0> Event
0 SAMP 1→0
1 INT0
2 Timer3
3* Timer5
4* CTMU
6* Alt. CTMU
7 Auto
* Available in select devices only.
Device Reset
Legend: HW = automatic hardware event; SW = software controlled event.
Note: See Register 17-1 for definitions of the ASAM, SAMP, DONE and SSRC<2:0> bits.
SW
HW
HW
ASAM 0→1 or
PIC24F Family Reference Manual
DS39705B-page 17-6 © 2009 Microchip Technology Inc.
17.3 REGISTERS
The 10-bit A/D Converter module uses a total of 22 registers for its operation. All registers are
mapped in the data memory space.
17.3.1 Control Registers
Depending on the specific device, the module has up to eight control and status registers:
• AD1CON1: A/D Control Register 1
• AD1CON2: A/D Control Register 2
• AD1CON3: A/D Control Register 3
• AD1CHS: A/D Input Channel Select Register
• AD1PCFG(L) and AD1PCFGH: A/D Port Configuration Registers
• AD1CSSL and AD1CSSH: A/D Input Scan Select Registers
The AD1CON1, AD1CON2 and AD1CON3 registers (Register 17-1, Register 17-2 and
Register 17-3) control the overall operation of the A/D module. This includes enabling the
module, configuring the conversion clock and voltage reference sources, selecting the sampling
and conversion triggers, and manually controlling the sample/convert sequences.
The AD1CHS register (Register 17-4) selects the input channels to be connected to the S/H
amplifier. It also allows the choice of input multiplexers and the selection of a reference source
for differential sampling.
The AD1PCFG (AD1PCFGL in select devices) register (Register 17-5) configures I/O pins as
analog inputs or digital I/Os. For PIC24F devices with the internal reference channels, the
PFCG<17:16> bits in the AD1PCFGH register (Register 17-6) enable these channels for
inclusion in sequential scanning.
The AD1CSSL register (Register 17-7) selects the channels to be included for sequential
scanning. For PIC24F devices with the internal reference channels, the AD1CSSH register
(Register 17-8) selects these channels for inclusion in sequential scanning.
17.3.2 A/D Result Buffers
The module incorporates a 16-word, dual port RAM, called ADC1BUF, to store the A/D results.
Each of the locations is mapped into the data memory space and is separately addressable. The
16 buffer locations are referred to as ADC1BUF0 through ADC1BUFF. The A/D result buffers are
read-only.
© 2009 Microchip Technology Inc. DS39705B-page 17-7
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
Register 17-1: AD1CON1: A/D Control Register 1
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
ADON — ADSIDL — — — FORM1 FORM0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/C-0, HCS
SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE
bit 7 bit 0
Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit HCS = Hardware Clearable/Settable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADON: A/D Operating Mode bit
1 = A/D Converter module is operating
0 = A/D Converter is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9-8 FORM<1:0>: Data Output Format bits
11 = Signed fractional (sddd dddd dd00 0000)
10 dddd dddd dd00 0000 = Fractional ( )
01 = Signed integer (ssss sssd dddd dddd)
00 = Integer (0000 00dd dddd dddd)
bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits (event ends sampling and starts conversion)
111 = Internal counter (auto-convert)
110 = CTMU event (when not implemented as ‘100’)(1)
101 = Reserved
100 = CTMU event(1)
011 = Timer5 compare match(1,2)
010 = Timer3 compare match(2)
001 = Active transition on INT0 pin (basic sync convert)
000 = Clearing SAMP bit (full program control)
bit 4-3 Unimplemented: Read as ‘0’
bit 2 ASAM: A/D Sample Auto-Start Mode bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: A/D Sample Enable Mode Mode bit
1 = A/D Sample-and-Hold amplifier is sampling
0 = A/D Sample-and-Hold amplifier is holding
When ASAM = 0, writing ‘1’ to this bit starts sampling. When SSRC<2:0> = 000, writing ‘0’ to this bit
will end sampling and start conversion.
bit 0 DONE: A/D Conversion Status bit
1 = A/D conversion is done
0 = A/D conversion is not done or has not started
Clearing this bit will not affect any operation in progress; it is cleared by software or start of a new conversion.
Note 1: This option is available in select devices only. Refer to the specific device data sheet.
2: Use Timer3 or Timer5 as a clock divider for a fixed sample rate. The T3CK or T5CK input may also be
selected with this mode to synchronize with an external event by configuring the counter to clock from the
T3CK pin while preset for one pulse. See Section 14. “Timers” for more information.
PIC24F Family Reference Manual
DS39705B-page 17-8 © 2009 Microchip Technology Inc.
Register 17-2: AD1CON2: A/D Control Register 2
R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 U-0 U-0
VCFG2 VCFG1 VCFG0 r — —— CSCNA
bit 15 bit 8
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS(1) — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
bit 12 Reserved: Maintain as ‘0’
bit 11 Unimplemented: Read as ‘0’
bit 10 CSCNA: MUX A Channel Scan/Input Channel Select bit
1 = Scan inputs selected by the AD1CSSL register as the MUX A input
0 = Use the channel selected by the CH0SA bits as the MUX A input
bit 9-8 Unimplemented: Read as ‘0’
bit 7 BUFS: Buffer Fill Status bit(1)
1 = A/D is currently filling ADC1BUF8-ADC1BUFF, user should access data in ADC1BUF0-ADC1BUF7
0 = A/D is currently filling ADC1BUF0-ADC1BUF7, user should access data in ADC1BUF8-ADC1BUFF
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
.....
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers (ADC1BUF0 to ADC1BUF7 and ADC1BUF8 to
ADC1BUFF)
0 = Buffer configured as one 16-word buffer (ADC1BUF0 to ADC1BUFF)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Alternate between MUX A and MUX B input multiplexer settings on successive conversions,
starting with MUX A
0 = Always uses MUX A input multiplexer settings
Note 1: Only valid when ADC1BUF is functioning as two buffers (BUFM = 1).
VCFG<2:0> VR+ VR-
000 AVDD AVSS
001 External VREF+ Pin AVSS
010 AVDD External VREF- Pin
011 External VREF+ Pin External VREF- Pin
1xx AV AVDD SS
© 2009 Microchip Technology Inc. DS39705B-page 17-9
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
Register 17-3: AD1CON3: A/D Control Register 3
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: A/D Conversion Clock Source bit
1 = A/D internal RC clock
0 = Clock derived from system clock
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
11111 = 31 TAD
·····
00001 = 1 TAD
00000 = 0 TAD (not recommended)
bit 7-0 ADCS<7:0>: A/D Conversion Clock Period Select bits(1)
11111111
······ = Reserved
01000000
00111111 = 64 • Tcy
······
00000001 = 2 • TCY
00000000 = TCY
Note 1: Only valid when using the system clock as the conversion clock (ADRC = 0).
PIC24F Family Reference Manual
DS39705B-page 17-10 © 2009 Microchip Technology Inc.
Register 17-4: AD1CHS: A/D Input Channel Select Register
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB — — CH0SB4(1) CH0SB3 CH0SB2 CH0SB1 CH0SB0
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA — — CH0SA4(1) CH0SA3 CH0SA2 CH0SA1 CH0SA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: S/H Amplifier Negative Input Select for MUX B Multiplexer Setting bit
1 = Negative input is AN1
0 = Negative input is VR-
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 CH0SB<4:0>: S/H Amplifier Positive Input Select for MUX B Multiplexer Setting bits
(1)
The number of implemented analog inputs and the bit combinations assigned to them vary significantly
between device families. In general, external analog inputs, AN0 through AN15 (where implemented),
are sequentially assigned from ‘00000’ as shown below. If a sequential input is unimplemented, its
corresponding bit value is also unimplemented.
In addition, some devices implement inputs for internal band gap references, external voltage
references, and other analog modules, such as the CTMU. Refer to the specific device data sheet for
a complete listing of implemented inputs for a particular device.
Any bit combinations not explicitly listed are unimplemented. Using an unimplemented channel for a
conversion will produce unpredictable results.
01111 = Positive input is AN15
01110 = Positive input is AN14
01101 = Positive input is AN13
01100 = Positive input is AN12
01011 = Positive input is AN11
01010 = Positive input is AN10
01001 = Positive input is AN9
01000 = Positive input is AN8
00111 = Positive input is AN7
00110 = Positive input is AN6
00101 = Positive input is AN5
00100 = Positive input is AN4
00011 = Positive input is AN3
00010 = Positive input is AN2
00001 = Positive input is AN1
00000 = Positive input is AN0
bit 7 CH0NA: S/H Amplifier Negative Input Select for MUX A Multiplexer Setting bit
1 = Negative input is AN1
0 = Negative input is VR-
bit 6-5 Unimplemented: Read as ‘0’
bit 4-0 CH0SA<4:0>: S/H Amplifier Positive Input Select for MUX A Multiplexer Setting bits
(1)
Implemented combinations are identical to those for CH0SB<4:0>.
Note 1: CH0SB4 and CH0SA4 are implemented in select devices only. Their implementation generally indicates
an extended range of input sources from voltage references and other analog modules.
© 2009 Microchip Technology Inc. DS39705B-page 17-11
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
Register 17-5: AD1PCFG(L): A/D Port Configuration Low Register(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PCFG<15:0>: Analog Input Pin Configuration Control bits
1 = Pin for corresponding analog channel is in Digital mode; port read input enabled, A/D input
multiplexer input connected to AVSS
0 = Pin for corresponding analog channel is in Analog mode; port read input disabled, A/D module
samples pin voltage
Note 1: In devices without the internal band gap reference options, this register is named AD1PCFG. In devices
with the band gap options, it is named AD1PCFGL.
Register 17-6: AD1PCFGH: A/D Port Configuration High Register(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — PCFG17 PCFG16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-2 Unimplemented: Read as ‘0’
bit 1 PCFG17: A/D Input Band Gap Scan Enable bit
1 = Analog channel disabled from input scan
0 = Internal band gap (VBG) channel enabled for A/D MUX input
bit 0 PCFG16: A/D Input Half Band Gap Scan Enable bit
1 = Analog channel disabled from input scan
0 = Internal VBG/2 channel enabled for A/D MUX input
Note 1: AD1PCFGH is implemented in select devices only.
PIC24F Family Reference Manual
DS39705B-page 17-12 © 2009 Microchip Technology Inc.
Register 17-7: AD1CSSL: A/D Input Scan Select Low Register for MUX A(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CSSL<15:0>: A/D Input Channel Scan Selection bits
1 = Corresponding analog channel, ANx, is selected for sequential scanning on MUX A
0 = Corresponding analog channel is ignored in sequential scanning
Note 1: Only MUX A supports scanning of input channels.
Register 17-8: AD1CSSH: A/D Input Scan Select High Register for MUX A
(1,2)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — CSSL17 CSSL16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-2 Unimplemented: Read as ‘0’
bit 1 CSSL17: A/D Input Band Gap Scan Selection bit
1 = Internal band gap (VBG) channel is selected for sequential scanning on MUX A
0 = Analog channel is ignored in sequential scanning
bit 0 CSSL16: A/D Input Half Band Gap Scan Selection bit
1 = Internal VBG/2 channel is selected for sequential scanning on MUX A
0 = Analog channel is ignored in sequential scanning
Note 1: Only MUX A supports scanning of input channels.
2: AD1CSSH is implemented in select devices only.
PIC24F Family Reference Manual
DS39705B-page 17-14 © 2009 Microchip Technology Inc.
17.4.2 Selecting the A/D Conversion Clock
The A/D Converter has a maximum rate at which conversions may be completed. An analog
module clock, TAD, controls the conversion timing. The A/D conversion requires 12 clock periods
(12 TAD). The A/D clock is derived from the device instruction clock.
The period of the A/D conversion clock is software selected using a 6-bit counter. There are
64 possible options for TAD, specified by the ADCS bits in the AD1CON3 register. Equation 17-1
gives the TAD value as a function of the ADCS control bits and the device instruction cycle clock
period, TCY. For correct A/D conversions, the A/D conversion clock (TAD) must be selected to
ensure a minimum TAD time of 75 ns.
Equation 17-1: A/D Conversion Clock Period
The A/D Converter also has its own dedicated RC clock source that can be used to perform
conversions. The A/D RC clock source should be used when conversions are performed while
the device is in Sleep mode. The RC oscillator is selected by setting the ADRC bit
(AD1CON3<15>). When the ADRC bit is set, the ADCS bits have no effect on A/D operation.
17.4.3 Configuring Analog Port Pins
The AD1PCFG register (AD1PCFGL and AD1PCFGH registers in select devices) specifies the
input condition of device pins used as analog inputs. A pin is configured as an analog input when
the corresponding PCFGx bit (AD1PCFG<x>) is cleared. The register is cleared on device
Resets, causing the A/D input pins to be configured for analog inputs by default. When
configured for analog inputs, the associated port I/O digital input buffer is disabled, so it does not
consume current.
For external analog inputs, both the AD1PCFG(L) register and the corresponding TRIS register
bits control the operation of the A/D port pins. The port pins that will function as analog inputs
must also have their corresponding TRIS bits set, specifying the pins as inputs. After a device
Reset, all TRIS bits are set.
If the I/O pin associated with an A/D channel is configured as a digital output (TRIS bit is cleared),
while the pin is configured for Analog mode (AD1PCFG<x> = 0), the port digital output level (V
OH
or VOL) will be converted.
A pin is configured as digital I/O when the corresponding PCFGx bit is set. In this configuration,
the input to the analog multiplexer is connected to AVSS.
17.4.4 Input Channel Selection
The A/D Converter incorporates two independent sets of input multiplexers (MUX A and MUX B)
that allow users to choose which analog channels are to be sampled. The inputs specified by the
CH0SA bits and CH0NA are collectively called the MUX A inputs. The inputs specified by the
CH0SB bits and CH0NB are collectively called the MUX B inputs.
Note 1: When reading a PORT register, any pin configured as an analog input reads as ‘0’.
2: Analog levels on any pin that is defined as a digital input (including the AN<15:0>
pins) may cause the input buffer to consume current that is out of the device’s
specification.
TCY (ADCS + 1)
ADCS = – 1
TAD
TCY
Note: Based on TCY = 2/FOSC, Doze mode and PLL are disabled.
TAD =
PIC24F Family Reference Manual
DS39705B-page 17-16 © 2009 Microchip Technology Inc.
17.4.5 Enabling the Module
When the ADON bit (AD1CON1<15>) is set, the module is fully powered and functional. When
ADON is ‘0’, the module is disabled. The digital and analog portions of the circuit are turned off
for maximum current savings. As the ADC1BUF registers are also part of the A/D module,
clearing ADON may also result in a loss of conversion data.
When enabling the module by setting the ADON bit, the user must wait for the analog stages to
stabilize. For the stabilization time, refer to Section 17.16 “Electrical Specifications”.
17.5 INITIALIZATION
Example 17-1 shows a simple initialization code example for the A/D module. In this particular
configuration, all 16 analog input pins are set up as analog inputs. Operation in Idle mode is
disabled, output data is in unsigned fractional format, and AVDD and AVSS are used for VR+ and
VR-. The start of sampling, as well as the start of conversion (conversion trigger), are performed
directly in software. Scanning of inputs is disabled and an interrupt occurs after every
sample/convert sequence (1 conversion result) with only one channel (AN0) being converted. The
A/D conversion clock is TCY/2.
This example shows one method of controlling a sample/convert sequence by manually setting
and clearing the SAMP bit (AD1CON1<1>). This method, among others, is more fully dis-
cussed in Section 17.6 “Controlling the Sampling Process” and Section 17.7 “Controlling
the Conversion Process”.
Example 17-1: A/D Initialization Code Example
AD1PCFG = 0xFFFE; // Configure A/D port
// AN0 input pin is analog
AD1CON1 = 0x2202; // Configure sample clock source
// and conversion trigger mode.
// Unsigned Fraction format (FORM<1:0>=10),
// Manual conversion trigger (SSRC<2:0>=000),
// Manual start of sampling (ASAM=0),
// No operation in Idle mode (ADSIDL=1),
// S/H in Sample (SAMP = 1)
AD1CON2 = 0; // Configure A/D voltage reference
// and buffer fill modes.
// Vr+ and Vr- from AVdd and AVss (VCFG<2:0>=000),
// Inputs are not scanned,
// Interrupt after every sample
AD1CON3 = 0x0100; // Configure sample time = 1Tad,
// A/D conversion clock as Tcy
AD1CHS = 0; // Configure input channels,
// S/H+ input is AN0,
// S/H- input is Vr- (AVss).
AD1CSSL = 0; // No inputs are scanned.
IFS0bits.AD1IF = 0; // Clear A/D conversion interrupt.
// Configure A/D interrupt priority bits (AD1IP<2:0>) here, if
// required. Default priority level is 4.
IEC0bits.AD1IE = 1; // Enable A/D conversion interrupt
AD1CON1bits.ADON = 1; // Turn on A/D
AD1CON1bits.SAMP = 1; // Start sampling the input
Delay(); // Ensure the correct sampling time has elapsed
// before starting conversion.
AD1CON1bits.SAMP = 0; // End A/D sampling and start conversion
// Example code for A/D ISR:
void __attribute__ ((__interrupt__)) _ADC1Interrupt(void)
{
IFS0bits.AD1IF = 0;
}
© 2009 Microchip Technology Inc. DS39705B-page 17-17
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
17.6 CONTROLLING THE SAMPLING PROCESS
17.6.1 Manual Sampling
Setting the SAMP bit (AD1CON1<1>) while the ASAM bit (AD1CON1<2>) is clear causes the
A/D to begin sampling. Clearing the SAMP bit ends sampling and automatically begins the
conversion; however, there must be a sufficient delay between setting and clearing SAMP for the
sampling process to start (tPSS, parameter AD61). Sampling will not resume until the SAMP bit
is once again set. For an example, see Figure 17-4.
17.6.2 Automatic Sampling
Setting the ASAM bit causes the A/D to automatically begin sampling after a conversion has
been completed. One of several options can be used to end sampling and complete the conver-
sions. Sampling will continue on the next selected channel after the conversion in progress has
completed. For an example, see Figure 17-5.
17.6.3 Monitoring Sample Status
The SAMP bit indicates the sampling state of the A/D. Generally, when the SAMP bit clears,
indicating the end of sampling, the DONE bit is automatically cleared to indicate the start of
conversion. If SAMP is ‘0’ while DONE is ‘1’, the A/D is in an inactive state.
17.6.4 Aborting a Sample
While in Manual Sampling mode, clearing the SAMP bit will terminate sampling. If
SSRC<2:0> = 000, it may also start a conversion automatically.
Clearing the ASAM bit while in Automatic Sampling mode will not terminate an ongoing
sample/convert sequence; however, sampling will not automatically resume after a subsequent
conversion.
17.7 CONTROLLING THE CONVERSION PROCESS
The conversion trigger source will terminate sampling and start a selected sequence of
conversions. The SSRC<2:0> bits (AD1CON1<7:5>) select the source of the conversion trigger.
17.7.1 Manual Control
When SSRC<2:0> = 000, the conversion trigger is under software control. Clearing the SAMP
bit (AD1CON1<1>) starts the conversion sequence.
Figure 17-4 is an example where setting the SAMP bit initiates sampling, and clearing the SAMP
bit terminates sampling and starts conversion. The user software must time the setting and
clearing of the SAMP bit to ensure adequate sampling time of the input signal.
Figure 17-5 is an example where setting the ASAM bit initiates automatic sampling, and clearing
the SAMP bit terminates sampling and starts conversion. After the conversion completes, the
module sets the SAMP bit and returns to the sample state. The user software must time the
clearing of the SAMP bit to ensure adequate sampling time of the input signal, understanding that
the time since previously clearing the SAMP bit includes the conversion time which immediately
follows, as well as the next sampling time.
Note 1: The available conversion trigger sources may vary depending on the PIC24F
device variant. Please refer to the specific device data sheet for the available
conversion trigger sources.
2: The SSRC selection bits should not be changed when the A/D module is enabled.
If the user wishes to change the conversion trigger source, the A/D module should
be disabled first by clearing the ADON bit (AD1CON1<15>).
PIC24F Family Reference Manual
DS39705B-page 17-18 © 2009 Microchip Technology Inc.
Figure 17-4: Converting One Channel, Manual Sample Start, Manual Conversion Start
Example 17-2: Converting One Channel, Manual Sample Start, Manual Conversion Start Code
Figure 17-5: Converting One Channel, Automatic Sample Start, Manual Conversion Start
A/D CLK
SAMP
ADC1BUF0
TSAMP TCONV
BCF AD1CON1, SAMPBSF AD1CON1, SAMP
Instruction Execution
DONE
int ADCValue;
AD1PCFG = 0xFFFB; // AN2 as analog, all other pins are digital
AD1CON1 = 0x0000; // SAMP bit = 0 ends sampling and starts converting
AD1CHS = 0x0002; // Connect AN2 as S/H+ input
// in this example AN2 is the input
AD1CSSL = 0;
AD1CON3 = 0x0002; // Manual Sample, Tad = 3Tcy
AD1CON2 = 0;
AD1CON1bits.ADON = 1; // turn ADC ON
while (1) // repeat continuously
{
AD1CON1bits.SAMP = 1; // start sampling...
Delay(); // Ensure the correct sampling time has elapsed
// before starting conversion.
AD1CON1bits.SAMP = 0; // start converting
while (!AD1CON1bits.DONE){}; // conversion done?
ADCValue = ADC1BUF0; // yes then get ADC value
}
A/D CLK
SAMP
ADC1BUF0
TSAMP TCONV
BCF AD1CON1, SAMP
TCONV
BSF AD1CON1, ASAM BCF AD1CON1, SAMP
TSAMP
TAD0TAD0
Instruction Execution
© 2009 Microchip Technology Inc. DS39705B-page 17-21
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
17.7.3 Event Trigger Conversion Start
It is often desirable to synchronize the end of sampling and the start of conversion with some
other time event. The A/D module may use one of three sources as a conversion trigger event.
17.7.3.1 EXTERNAL INT0 PIN TRIGGER
When SSRC<2:0> = 001, the A/D conversion is triggered by an active transition on the INT0 pin.
The pin may be programmed for either a rising edge input or a falling edge input.
17.7.3.2 GENERAL PURPOSE TIMER COMPARE TRIGGER
The A/D is configured in this Trigger mode by setting SSRC<2:0> = 010. When a match occurs
between the 32-bit timer, TMR3/TMR2, and the 32-bit combined Period register, PR3/PR2, a
special ADC trigger event signal is generated by Timer3. Refer to Section 14. “Timers” for more
details.
In select devices, this feature is also implemented for the TMR5/TMR4 timer pair. Refer to the
specific device data sheet for details.
17.7.3.3 SYNCHRONIZING A/D OPERATIONS TO INTERNAL OR EXTERNAL
EVENTS
The modes where an external event trigger pulse ends sampling and starts conversion
(SSRC<2:0> = 001, 010 or 011) may be used in combination with auto-sampling (ASAM = 1) to
cause the A/D to synchronize the sample conversion events to the trigger pulse source. For
example, in Figure 17-9 where SSRC<2:0> = 010 and ASAM = 1, the A/D will always end sampling
and start conversions synchronously with the timer compare trigger event. The A/D will have a
sample conversion rate that corresponds to the timer comparison event rate.
Figure 17-8: Manual Sample Start, Conversion Trigger-Based Conversion Start
Figure 17-9: Auto-Sample Start, Conversion Trigger-Based Conversion Start
Conversion Trigger
A/D CLK
SAMP
ADC1BUF0
TSAMP TCONV
BSF AD1CON1, SAMP
Instruction Execution
Conversion Trigger
A/D CLK
SAMP
ADC1BUF0
TSAMP TCONV
BSF AD1CON1, ASAM
TCONVTSAMP
ADC1BUF1
DONE
Reset by
Software
Instruction Execution
PIC24F Family Reference Manual
DS39705B-page 17-26 © 2009 Microchip Technology Inc.
Example 17-7: Converting a Single Channel 16 Times per Interrupt
A/D Configuration:
• Select AN0 for S/H+ Input (CH0SA<3:0> = 0000)
• Select VR- for S/H- Input (CH0NA = 0)
• Configure for No Input Scan (CSCNA = 0)
• Use Only MUX A for Sampling (ALTS = 0)
• Set AD1IF on Every 16th Sample (SMPI<3:0> = 1111)
• Configure Buffers for Single, 16-Word Results (BUFM = 0)
Operational Sequence:
1. Sample MUX A Input AN0; Convert and Write to Buffer 0h
2. Sample MUX A Input AN0; Convert and Write to Buffer 1h
3. Sample MUX A Input AN0; Convert and Write to Buffer 2h
4. Sample MUX A Input AN0; Convert and Write to Buffer 3h
5. Sample MUX A Input AN0; Convert and Write to Buffer 4h
6. Sample MUX A Input AN0; Convert and Write to Buffer 5h
7. Sample MUX A Input AN0; Convert and Write to Buffer 6h
8. Sample MUX A Input AN0; Convert and Write to Buffer 7h
9. Sample MUX A Input AN0; Convert and Write to Buffer 8h
10. Sample MUX A Input AN0; Convert and Write to Buffer 9h
11. Sample MUX A Input AN0; Convert and Write to Buffer Ah
12. Sample MUX A Input AN0; Convert and Write to Buffer Bh
13. Sample MUX A Input AN0; Convert and Write to Buffer Ch
14. Sample MUX A Input AN0; Convert and Write to Buffer Dh
15. Sample MUX A Input AN0; Convert and Write to Buffer Eh
16. Sample MUX A Input AN0; Convert and Write to Buffer Fh
17. Set AD1IF Flag (and generate interrupt, if enabled)
18. Repeat (1-16) after Return from Interrupt
Results Stored in Buffer (after 2 cycles):
Buffer
Address
Buffer Contents
at 1st AD1IF Event
Buffer Contents
at 2nd AD1IF Event
ADC1BUF0 AN0, Sample 1 AN0, Sample 17
ADC1BUF1 AN0, Sample 2 AN0, Sample 18
ADC1BUF2 AN0, Sample 3 AN0, Sample 19
ADC1BUF3 AN0, Sample 4 AN0, Sample 20
ADC1BUF4 AN0, Sample 5 AN0, Sample 21
ADC1BUF5 AN0, Sample 6 AN0, Sample 22
ADC1BUF6 AN0, Sample 7 AN0, Sample 23
ADC1BUF7 AN0, Sample 8 AN0, Sample 24
ADC1BUF8 AN0, Sample 9 AN0, Sample 25
ADC1BUF9 AN0, Sample 10 AN0, Sample 26
ADC1BUFA AN0, Sample 11 AN0, Sample 27
ADC1BUFB AN0, Sample 12 AN0, Sample 28
ADC1BUFC AN0, Sample 13 AN0, Sample 29
ADC1BUFD AN0, Sample 14 AN0, Sample 30
ADC1BUFE AN0, Sample 15 AN0, Sample 31
ADC1BUFF AN0, Sample 16 AN0, Sample 32
Produkt Specifikationer
| Mærke: | Microchip |
| Kategori: | Ikke kategoriseret |
| Model: | PIC24FJ64GA002 |
Har du brug for hjælp?
Hvis du har brug for hjælp til Microchip PIC24FJ64GA002 stil et spørgsmål nedenfor, og andre brugere vil svare dig
Ikke kategoriseret Microchip Manualer
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
Ikke kategoriseret Manualer
- EGO
- RCA
- Liemke
- EasyMaxx
- Strymon
- Videotel Digital
- Burley
- HTC
- ASA
- Icy Dock
- Texas
- Atomos
- Betty Bossi
- Viltrox
- Comprehensive
Nyeste Ikke kategoriseret Manualer
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025
17 Juni 2025