Microchip SY58020U Manual

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Side 1/13

SY58020U

6GHz, 1:4 CML Fanout Buffer/Translator

with Internal I/O Termination

P . recision Edge is rademark f Micrel, Inc a t o

Micrel Inc. • 2180 Fortune Drive • Jose, CA 95131 • USA • tel +1 (408) 944 0800 • fax + 1 (408) 474 1000 • San - - http://www.micrel.com

October 27

, 2014 Revision 5.0

tcghelp@micrel.com -or (408) 955 1690

General Description

The SY58020U is a 2.5V/3.3V precision, high-speed, fully

differential 1:4 CML fanout buffer. Optimized to provide

four identical output copies with less than 15ps of skew

and 27fsRMS of typical additive phase jitter, the SY58020U

can process clock signals as fast as 6GHz.

The differential input includes Micrel’s unique, 3-pin input

termination architecture interfaces to differential that

LVPECL, LVDS, and CML signals (AC or DC coupled) as - -

small as 100mV without any level shifting or termination -

resistor networks in the signal path. For AC coupled input -

interface applications, an on output reference -board

voltage (VREF-AC) is provided to bias the VT pin. The outputs

are optimized to drive 400mV typical swing into 50Ω loads,

with extremely fast rise/fall times guaranteed to be less

than 60ps.

The SY58020U operates from a 2.5V ±5% supply or 3.3V

±10% supply and is guaranteed over the full industrial

temperature range ( 40°C to +85°C). For applications that –

require LVPECL outputs, consider the SY58021U or

SY58022U 1:4 fanout buffer with 800mV and 400mV

output swing, respectively. The SY58020U is part of

Micrel’s high-speed, Precision Edge® product line.

Datasheets and support documentation are available on

Micrel’s web site at: www.micrel.com.

Features

•Precision 1:4, 400mV CML fanout buffer

•Guaranteed AC performance over temperature/voltage:

−> 6GHz fMAX clock

−< 60ps tr / tf times

−< 250ps tpd

−< 15ps max. skew

•Low-jitter performance:

−27fsRMS typical additive phase jitter

•Accepts an input signal as low as 100mV

•Unique patented input termination and VT pin accepts

DC- -coupled and AC coupled differential inputs:

LVPECL, LVDS, and CML

•50Ω source terminated CML outputs

•Power supply 2.5V ±5% and 3.3V ±10%

•Industrial temperature range: –40°C to +85°C

•Available in 16-pin (3mm x 3mm) QFN package

Applications

•All SONET and All GigE clock distribution

•Fibre Channel clock and data distribution

•Backplane distribution

•Data distribution: OC- -48, OC 48+FEC, XAUI

•High-end, low skew, multiprocessor synchronous clock

distribution

Functional Block Diagram Typical Performance

Micrel, Inc.

SY58020U

October 27

, 2014 2 Revision 5.0

tcghelp@micrel.com -or (408) 955 1690

Ordering Information( )1

Part Number

Package Type

Operating Range

Package Marking

Lead Finish

SY58020UM 16G -QFN Industrial 020U with

Pb- -Free bar line indicator

Pb-Free

NiPdAu

SY58020UMG TR(2) - QFN 16 Industrial 020U with

Pb- -Free bar line indicator

Pb-Free

NiPdAu

Note:

1. 25 Contact factory for die availability. Dice are guaranteed at TA = °C, DC electrical only.

2. Tape and Reel.

Pin Conguration

16- - Pin QFN (QFN 16)

Pin Description

Pin Number

Pin Name

Pin Function

1 , 4 IN, /IN

Differential Input: This input pair receives the signal to be buffered. Each pin of this pair internally

terminates with 50Ω to the V

T pin. Note that this input will default to an indeterminate state if left

open. See “Input Interface Applications” section.

2 VT

Input Termination Center Tap: Each input terminates to this pin. The V- T pin provides a center p -ta

for each input (IN, /IN) to the termination network for maximum interface flexibility. See “Input

Interface Applications” section.

3 VREF-AC

Reference Output Voltage: This output biases to V

CC-1.2V. It is used when AC-coupling to

differential inputs. Connect VREF-AC directly to the VT pin. Bypass with 0.01 F low ESR capacitor µ

to VCC. See “Input Interface Applications” section.

8, 13 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the pins as

possible.

5, 16 GND,

Exposed Pad

Ground. Exposed pad must be connected to a ground plane that is the same potential as the

ground pin.

14, 15

11, 12

9, 10

6, 7

/Q0, Q0,

/Q1, Q1,

/Q2, Q2,

/Q3, Q3

CML Differential Output Pairs: Differential buffered output copy of the input signal. The output

swing is typically 400mV into 50Ω load. Normally terminate CML output pairs with 100Ω across Q

and /Q outputs at the receiving end. Unused output pairs may be left floating with no impact on

jitter or skew. See “CML Output Termination” section.

Produkt Specifikationer

Mærke:	Microchip
Kategori:	Ikke kategoriseret
Model:	SY58020U

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