General Description
The SY58020U is a 2.5V/3.3V precision, high-speed, fully
differential 1:4 CML fanout buffer. Optimized to provide
four identical output copies with less than 15ps of skew
and 27fsRMS of typical additive phase jitter, the SY58020U
can process clock signals as fast as 6GHz.
The differential input includes Micrel’s unique, 3-pin input
termination architecture interfaces to differential that
LVPECL, LVDS, and CML signals (AC or DC coupled) as - -
small as 100mV without any level shifting or termination -
resistor networks in the signal path. For AC coupled input -
interface applications, an on output reference -board
voltage (VREF-AC) is provided to bias the VT pin. The outputs
are optimized to drive 400mV typical swing into 50Ω loads,
with extremely fast rise/fall times guaranteed to be less
than 60ps.
The SY58020U operates from a 2.5V ±5% supply or 3.3V
±10% supply and is guaranteed over the full industrial
temperature range ( 40°C to +85°C). For applications that –
require LVPECL outputs, consider the SY58021U or
SY58022U 1:4 fanout buffer with 800mV and 400mV
output swing, respectively. The SY58020U is part of
Micrel’s high-speed, Precision Edge® product line.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
•Precision 1:4, 400mV CML fanout buffer
•Guaranteed AC performance over temperature/voltage:
−> 6GHz fMAX clock
−< 60ps tr / tf times
−< 250ps tpd
−< 15ps max. skew
•Low-jitter performance:
−27fsRMS typical additive phase jitter
•Accepts an input signal as low as 100mV
•Unique patented input termination and VT pin accepts
DC- -coupled and AC coupled differential inputs:
LVPECL, LVDS, and CML
•50Ω source terminated CML outputs
•Power supply 2.5V ±5% and 3.3V ±10%
•Industrial temperature range: –40°C to +85°C
•Available in 16-pin (3mm x 3mm) QFN package
Applications
•All SONET and All GigE clock distribution
•Fibre Channel clock and data distribution
•Backplane distribution
•Data distribution: OC- -48, OC 48+FEC, XAUI
•High-end, low skew, multiprocessor synchronous clock
distribution
Functional Block Diagram Typical Performance