Microchip PIC24HJ128GP502 Manual

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© 2007 Microchip Technology Inc. DS70225B-page 16-1
ADC
16
Section 16. Analog-to-Digital Converter (ADC)
HIGHLIGHTS
This section of the manual contains the following major topics:
16.1 Introduction .................................................................................................................. 16-2
16.2 Control Registers ......................................................................................................... 16-4
16.3 A/D Terminology and Conversion Sequence ............................................................. 16-14
16.4 ADC Module Configuration ........................................................................................ 16-16
16.5 Selecting the Voltage Reference Source ................................................................... 16-16
16.6 Selecting the A/D Conversion Clock .......................................................................... 16-17
16.7 Selecting Analog Inputs for Sampling ........................................................................ 16-18
16.8 Enabling the Module .................................................................................................. 16-20
16.9 Specifying Sample/Conversion Control...................................................................... 16-20
16.10 How to Start Sampling ............................................................................................... 16-21
16.11 How to Stop Sampling and Start Conversions ........................................................... 16-22
16.12 Controlling Sample/Conversion Operation................................................................. 16-32
16.13 Specifying Conversion Results Buffering ................................................................... 16-33
16.14 Conversion Sequence Examples............................................................................... 16-37
16.15 A/D Sampling Requirements...................................................................................... 16-55
16.16 Reading the ADC Result Buffer ................................................................................. 16-56
16.17 Transfer Function (10-bit Mode)................................................................................. 16-58
16.18 Transfer Function (12-bit Mode)................................................................................. 16-59
16.19 ADC Accuracy/Error................................................................................................... 16-60
16.20 Connection Considerations........................................................................................16-60
16.21 Code Examples.......................................................................................................... 16-60
16.22 Operation During Sleep and Idle Modes.................................................................... 16-67
16.23 Effects of a Reset....................................................................................................... 16-68
16.24 Special Function Registers Associated with the ADC................................................ 16-68
16.25 Design Tips ................................................................................................................ 16-70
16.26 Related Application Notes.......................................................................................... 16-71
16.27 Revision History ......................................................................................................... 16-72
© 2007 Microchip Technology Inc. DS70225B-page 16-2
Section 16. Analog-to-Digital Converter (ADC)
ADC
16
16.1 INTRODUCTION
The PIC24H family devices have up to 32 A/D input channels. These devices also have up to two
ADC modules (ADCx, where x = 1 or 2), each with its own set of Special Function Registers
(SFRs).
The 10-bit or 12-bit Operation Mode (AD12B) bit in the ADCx Control 1(ADxCON1) register
allows each of the ADC modules to be configured by the user application as either a 10-bit,
4 Sample/Hold (S/H) ADC (default configuration) or a 12-bit, 1 Sample/Hold ADC.
The 10-bit ADC configuration (AD12B = ) has the following key features:0
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 32 analog input pins
• External voltage reference input pins
• Simultaneous sampling of up to four analog input pins
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
• DMA support, including Peripheral Indirect Addressing
• Four result alignment options (signed/unsigned, fractional/integer)
• Operation during CPU Sleep and Idle modes
Depending on the particular device pinout, the ADC can have up to 32 analog input pins,
designated AN0 through AN31. In addition, there are two analog input pins for external voltage
reference connections. These voltage reference inputs can be shared with other analog input
pins. The actual number of analog input pins and external voltage reference input configuration
will depend on the specific device. For further details, refer to the device data sheet.
The analog inputs are multiplexed to four Sample/Hold amplifiers, designated CH0-CH3. One,
two, or four of the Sample/Hold amplifiers can be enabled for acquiring input data. The analog
input multiplexers can be switched between two sets of analog inputs during conversions.
Unipolar differential conversions are possible on all channels using certain input pins (refer to
Figure 16-1).
An Analog Input Scan mode can be enabled for the CH0 Sample/Hold Amplifier. A Control
register specifies which analog input channels are included in the scanning sequence.
The ADC is connected to a single-word result buffer; however, multiple conversion results can
be stored in a DMA RAM buffer with no CPU overhead. Each conversion result is converted to
one of four 16-bit output formats when it is read from the buffer.
The 12-bit ADC configuration (AD12B = 1) supports all the features described, except:
• In the 12-bit configuration, conversion speeds of up to 500 ksps are supported
• There is only one Sample/Hold amplifier in the 12-bit configuration, so simultaneous
sampling of multiple channels is not supported
Note: The ADC module needs to be disabled before the AD12B bit is modified.
© 2007 Microchip Technology Inc. DS70225B-page 16-12
Section 16. Analog-to-Digital Converter (ADC)
ADC
16
Register 16-7: AD1CSSH: ADC1 Input Scan Select Register High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CSS<31:16>: ADC Input Scan Selection bits(1, 2)
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1: On devices with less than 32 analog inputs, all ADxCSSL bits can be selected by user. However, inputs
selected for scan without a corresponding input on device convert VREF-.
2: ADC 2 only supports analog inputs AN0-AN15; therefore, no ADC 2 Input Scan Select register exists.
Register 16-8: ADxCSSL: ADCx Input Scan Select Register Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CSS<15:0>: ADC Input Scan Selection bits(1, 2)
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1: On devices with less than 16 analog inputs, all ADxCSSL bits can be selected by the user; however, inputs
selected for scan without a corresponding input on device convert VREF-.
2: The ‘x’ in ADxCSSL and ADCx refers to ADC 1 or ADC 2.
PIC24H Family Reference Manual
DS70225B-page 16-17 © 2007 Microchip Technology Inc.
16.6 SELECTING THE A/D CONVERSION CLOCK
The ADC module has a maximum rate at which conversions can be completed. An analog
module clock, TAD, controls the conversion timing. The A/D conversion requires 12 clock periods
(12 TAD) in the 10-bit mode and 14 clock periods (14 TAD) in the 12-bit mode. The A/D conversion
clock is derived from either the device instruction clock or an internal RC clock source.
The period of the A/D conversion clock is software selected using a 6-bit counter. There are 256
possible options for TAD, specified by the ADC Conversion Clock Select (ADCS<7:0>) bits
(ADxCON3<7:0>). Equation 16-1 gives the TAD value as a function of the ADCS control bits and
the device instruction cycle clock period, TCY.
Equation 16-1: A/D Conversion Clock Period
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a
minimum TAD time of 75 nsec.
The ADC module has a dedicated internal RC clock source that can be used to perform
conversions. The internal RC clock source should be used when A/D conversions are performed
while the device is in Sleep mode. The internal RC oscillator is selected by setting the ADC
Conversion Clock Source (ADRC) bit (ADxCON3<15>). When the ADRC bit is set, the
ADCS<7:0> bits have no effect on the A/D operation.
Figure 16-4: A/D Conversion Clock Period Block Diagram
TAD = TCY(ADCS + 1)
ADCS = TAD
TCY
– 1
0
1
ADC Internal
RC Clock
Clock Multiplier
1, 2, 3, 4, 5,..., 256
ADxCON3<15>
TCY
TAD
8
ADxCON3<7:0>
A/D Conversion
© 2007 Microchip Technology Inc. DS70225B-page 16-18
Section 16. Analog-to-Digital Converter (ADC)
ADC
16
16.7 SELECTING ANALOG INPUTS FOR SAMPLING
All Sample/Hold Amplifiers have analog multiplexers (refer to Figure 16-1) on both their
non-inverting and inverting inputs to select which analog input(s) are sampled. Once the
sample/convert sequence is specified, the ADxCHS0 and ADxCHS123 registers determine
which analog inputs are selected for each sample.
Additionally, the selected inputs can vary on an alternating sample basis or on a repeated
sequence of samples.
The same analog input can be connected to two or more Sample/Hold channels to improve
conversion rates.
16.7.1 Configuring Analog Port Pins
The ADPCFGH and ADPCFGL registers specify the input condition of device pins used as
analog inputs. Along with the Data Direction (TRISx) register in the Parallel I/O Port module,
these registers control the operation of the ADC pins.
A pin is configured as analog input when the corresponding PCFGn bit (ADPCFGH<n> or
ADPCFGL<n>) is clear. The ADPCFGH and ADPCFGL registers are clear at Reset, causing the
ADC input pins to be configured for analog input by default at Reset.
When configured for analog input, the associated port I/O digital input buffer is disabled so it does
not consume current.
The port pins that are desired as analog inputs must have their corresponding TRIS bit set,
specifying port input. If the I/O pin associated with an A/D input is configured as an output, the
TRIS bit is cleared and the port’s digital output level (VOH or VOL) is converted. After a device
Reset, all TRIS bits are set.
A pin is configured as digital I/O when the corresponding PCFGn bit is set. In this configuration,
the input to the analog multiplexer is connected to AVss.
16.7.2 Channel 0 Input Selection
Channel 0 is the most flexible of the four Sample/Hold channels in terms of selecting analog
inputs. It allows you to select any of the up to 16 analog inputs as the input to the positive input
of the channel. The Channel 0 Positive Input Select for Sample A (CH0SA<4:0>) bits
(ADxCHS0<4:0>) normally select the analog input for the positive input of channel 0.
You can select either VREF- or AN1 as the negative input of the channel. The CH0NA bit
(ADxCHS0<7>) normally selects the analog input for the negative input of channel 0.
16.7.2.1 SPECIFYING ALTERNATING CHANNEL 0 INPUT SELECTIONS
The Alternate Input Sample Mode Select (ALTS) bit (ADxCON2<0>) causes the ADC module to
alternate between two sets of inputs selected during successive samples.
The inputs specified by CH0SA<4:0> (ADxCHS0<4:0>), CH0NA (ADxCHS0<7>), CH123SA
(ADxCHS123<0>) and CH123NA<1:0> (ADxCHS123<2:1>) are collectively called the MUX A
inputs. The inputs specified by CH0SB<4:0> (ADxCHS0<12:8>), CH0NB (ADxCHS0<15>),
CH123SB (ADxCHS0<8>) and CH123NB<1:0> (ADxCHS0<10:9>) are collectively called the
MUX B inputs. When the ALTS bit is ‘1’, the ADC module alternates between the MUX A inputs
on one group of samples and the MUX B inputs on the subsequent group of samples.
Note: Different devices have different numbers of analog inputs. Verify the analog input
availability against the device data sheet.
Note 1: When the ADC Port register is read, any pin configured as an analog input reads
as a ‘0’.
2: Analog levels on any pin that is defined as a digital input (including the AN15:AN0
pins) may cause the input buffer to consume current that is out of the device’s
specification.
© 2007 Microchip Technology Inc. DS70225B-page 16-20
Section 16. Analog-to-Digital Converter (ADC)
ADC
16
16.7.3.1 SELECTING MULTIPLE CHANNELS FOR A SINGLE ANALOG INPUT
The analog input multiplexer can be configured so that the same input pin is connected to two or
more Sample/Hold channels. The ADC converts the value held on one Sample/Hold channel,
while the second Sample/Hold channel acquires a new input sample.
16.7.3.2 SPECIFYING ALTERNATING CHANNEL 1, 2 AND 3 INPUT
SELECTIONS
As with the channel 0 inputs, the ALTS bit (ADxCON2<0>) causes the ADC module to alternate
between two sets of inputs that are selected during successive samples for channel 1,2 and 3.
The MUX A inputs specified by CH123SA and CH123NA<1:0> always select the input when
ALTS = 0.
The MUX A inputs alternate with the MUX B inputs specified by CH123SB and CH123NB<1:0>
when ALTS = 1.
16.8 ENABLING THE MODULE
When the ADC Operating Mode (ADON) bit (ADxCON1<15>) is ‘1’, the ADC module is in Active
mode and is fully powered and functional.
When ADON is ‘0’, the ADC module is disabled. The digital and analog portions of the circuit are
turned off for maximum current savings.
In order to return to the Active mode from the Off mode, the user must wait for the analog stages
to stabilize. For the stabilization time, refer to the Electrical Characteristics section of the device
data sheet.
16.9 SPECIFYING SAMPLE/CONVERSION CONTROL
The ADC module uses four Sample/Hold amplifiers and one A/D Converter in the 10-bit mode.
The module can perform 1, 2 or 4 input samples and A/D conversions per sample/convert
sequence.
16.9.1 Number of Sample/Hold Channels
The CHPS<1:0> control bits (ADxCON2<9:8>) select how many Sample/Hold amplifiers are
used by the ADC module during sample/conversion sequences. The following three options can
be selected:
• CH0 only
• CH0 and CH1
• CH0, CH1, CH2, CH3
The CHPS control bits work in conjunction with the SIMSAM (simultaneous sample) control bit
(ADxCON1<3>). The CHPS and SIMSAM bits are not relevant in 12-bit mode as there is only
one Sample/Hold amplifier.
16.9.2 Simultaneous Sampling Enable
Some applications can require that multiple signals be sampled simultaneously. Table 16-1
shows the SIMSAM control bit (ADxCON1<3>) works in conjunction with the CHPS control bits
and controls the sample/convert sequence for multiple channels. The SIMSAM control bit has no
effect on the ADC module operation if CHPS<1:0> = 00. If more than one Sample/Hold amplifier
is enabled by the CHPS control bits and the SIMSAM bit is ‘0’, the two or four selected channels
are sampled and converted sequentially with two or four sampling periods. If the SIMSAM bit is
‘1’, two or four selected channels are sampled simultaneously with one sampling period. The
channels are then converted sequentially. The SIMSAM bit is not relevant in 12-bit mode as there
is only one S/H.
Note: The SSRC<2:0>, SIMSAM, ASAM, CHPS<1:0>, SMPI<3:0>, BUFM and ALTS bits,
as well as the ADxCON3, ADxCSSH and ADxCSSL registers, should not be written
to while ADON = 1. This leads to indeterminate results.

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Model: PIC24HJ128GP502

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